JPS5516450A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5516450A
JPS5516450A JP8945478A JP8945478A JPS5516450A JP S5516450 A JPS5516450 A JP S5516450A JP 8945478 A JP8945478 A JP 8945478A JP 8945478 A JP8945478 A JP 8945478A JP S5516450 A JPS5516450 A JP S5516450A
Authority
JP
Japan
Prior art keywords
bonding wire
tab
contact
corner
apt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8945478A
Other languages
Japanese (ja)
Inventor
Koichi Kiyozuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8945478A priority Critical patent/JPS5516450A/en
Publication of JPS5516450A publication Critical patent/JPS5516450A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid the contact between the tab and bonding wire by cutting the corner which us apt to contact with the bonding wire connected on the semiconductor pellet side of the tab. CONSTITUTION:A corner cut portion 4 is formed between either of main surfaces 111 and 112 of a tab 1 and a side surface 113 connecting the. this portion is formed at least at the crossing portion with a bonding wire 3. With this arrangement, the contact between the bonding wire 3 and the tab 11 is surely avoided even when the bonding wire 3 becomes loose ir too tight, because the corner of the tab 11 which is most apt to contact with the bonding wire 3 has been cut.
JP8945478A 1978-07-24 1978-07-24 Semiconductor device Pending JPS5516450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8945478A JPS5516450A (en) 1978-07-24 1978-07-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8945478A JPS5516450A (en) 1978-07-24 1978-07-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5516450A true JPS5516450A (en) 1980-02-05

Family

ID=13971133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8945478A Pending JPS5516450A (en) 1978-07-24 1978-07-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5516450A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191652U (en) * 1982-06-15 1983-12-20 三菱電機株式会社 Frame for semiconductor devices
JPH04142767A (en) * 1990-10-03 1992-05-15 Nec Corp Lead frame for semiconductor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5496366A (en) * 1978-01-17 1979-07-30 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5496366A (en) * 1978-01-17 1979-07-30 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191652U (en) * 1982-06-15 1983-12-20 三菱電機株式会社 Frame for semiconductor devices
JPH04142767A (en) * 1990-10-03 1992-05-15 Nec Corp Lead frame for semiconductor

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