JPS5496366A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5496366A
JPS5496366A JP271678A JP271678A JPS5496366A JP S5496366 A JPS5496366 A JP S5496366A JP 271678 A JP271678 A JP 271678A JP 271678 A JP271678 A JP 271678A JP S5496366 A JPS5496366 A JP S5496366A
Authority
JP
Japan
Prior art keywords
lead
electrodes
prevent
thin wire
metal thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP271678A
Other languages
Japanese (ja)
Inventor
Shinichi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP271678A priority Critical patent/JPS5496366A/en
Publication of JPS5496366A publication Critical patent/JPS5496366A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To form the electrode of the element in such a way that the metal wiring to be connected to the lead may not touch the semiconductor element installing table by forming the lacking part at the edge of the table, and thus to prevent the leakage or short circuit between electrodes.
CONSTITUTION: The lead frame is formed centering on element installing table 11a and with lead 11b, 11c and others distributed on the plane of nearly the same level as table 11a. Then lacking part 11x is formed through the press formation at the circumference of the main surface of table 11a of part 11 of the frame. Thus, semiconductor element 2 is connected to table 11a via electrode 3, and other electrodes 3b, 3c and others are connected to corresponding leads 11b, 11c and others via metal thin wire 4b, 4c and others. As a result, the metal thin wire approaches table 11a to prevent the undesired contact.
COPYRIGHT: (C)1979,JPO&Japio
JP271678A 1978-01-17 1978-01-17 Semiconductor device Pending JPS5496366A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP271678A JPS5496366A (en) 1978-01-17 1978-01-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP271678A JPS5496366A (en) 1978-01-17 1978-01-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5496366A true JPS5496366A (en) 1979-07-30

Family

ID=11537022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP271678A Pending JPS5496366A (en) 1978-01-17 1978-01-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5496366A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516450A (en) * 1978-07-24 1980-02-05 Hitachi Ltd Semiconductor device
JPS58191652U (en) * 1982-06-15 1983-12-20 三菱電機株式会社 Frame for semiconductor devices
JPH08316264A (en) * 1996-04-05 1996-11-29 Hitachi Ltd Semiconductor device and method for forming the same
JP2001345414A (en) * 2000-06-01 2001-12-14 Seiko Epson Corp Lead frame, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516450A (en) * 1978-07-24 1980-02-05 Hitachi Ltd Semiconductor device
JPS58191652U (en) * 1982-06-15 1983-12-20 三菱電機株式会社 Frame for semiconductor devices
JPH08316264A (en) * 1996-04-05 1996-11-29 Hitachi Ltd Semiconductor device and method for forming the same
JP2001345414A (en) * 2000-06-01 2001-12-14 Seiko Epson Corp Lead frame, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment

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