JPS55165673A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS55165673A JPS55165673A JP7372179A JP7372179A JPS55165673A JP S55165673 A JPS55165673 A JP S55165673A JP 7372179 A JP7372179 A JP 7372179A JP 7372179 A JP7372179 A JP 7372179A JP S55165673 A JPS55165673 A JP S55165673A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- type
- base layer
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/34—Bipolar devices
- H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
Landscapes
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To improve the withstand voltage by forming the base layer of a laminate body of high and low concentration impurities when the base layer is provided on the collector layer and the emitter region is formed in the base layer to obtain an asymmetric diffused junction transistor. CONSTITUTION:The N-type layers 1 to be the collector region are formed on both sides of the P-type Si substrate 2 to be the base region by the diffusion method, and one side layer 1 is polished and removed. Next a P-type impurity is diffused from the surface of the exposed substrate 1 to form the P<+>-type base layer 2', the base layer wherein the layers 2 and 2' are laminated is obtained. After this, both sides of the substrate are coated with the SiO2 film 8, the aperture 9 is made in the layer 2' side and the N-type emitter region 3 is formed in the layer 2' by the diffusion method. Next the apertures are made in the SiO2 film 8' formed at this time and the left film 8 respectively, the Al electrodes 5, 6 are provided on respective regions and the electrode 4 is provided on the back of the layer 1, the groove 10 is shaped and a pellet is obtained by cutting the groove. In this way, the depletion layer from the base-collector junction is obstructed by the layer 2', the base-emitter junction 7 is not reached by the depletion layer, accordingly the withstanding voltage can be improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7372179A JPS55165673A (en) | 1979-06-12 | 1979-06-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7372179A JPS55165673A (en) | 1979-06-12 | 1979-06-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55165673A true JPS55165673A (en) | 1980-12-24 |
Family
ID=13526363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7372179A Pending JPS55165673A (en) | 1979-06-12 | 1979-06-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55165673A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7791928B2 (en) | 2008-08-12 | 2010-09-07 | International Business Machines Corporation | Design structure, structure and method of using asymmetric junction engineered SRAM pass gates |
| US8036022B2 (en) | 2008-08-12 | 2011-10-11 | International Business Machines Corporation | Structure and method of using asymmetric junction engineered SRAM pass gates, and design structure |
| JP2015204301A (en) * | 2014-04-10 | 2015-11-16 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
-
1979
- 1979-06-12 JP JP7372179A patent/JPS55165673A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7791928B2 (en) | 2008-08-12 | 2010-09-07 | International Business Machines Corporation | Design structure, structure and method of using asymmetric junction engineered SRAM pass gates |
| US8036022B2 (en) | 2008-08-12 | 2011-10-11 | International Business Machines Corporation | Structure and method of using asymmetric junction engineered SRAM pass gates, and design structure |
| JP2015204301A (en) * | 2014-04-10 | 2015-11-16 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US9755037B2 (en) | 2014-04-10 | 2017-09-05 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing semiconductor device |
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