JPS5543843A - Semiconductor wafer and exposure mask for process thereof - Google Patents

Semiconductor wafer and exposure mask for process thereof

Info

Publication number
JPS5543843A
JPS5543843A JP11652578A JP11652578A JPS5543843A JP S5543843 A JPS5543843 A JP S5543843A JP 11652578 A JP11652578 A JP 11652578A JP 11652578 A JP11652578 A JP 11652578A JP S5543843 A JPS5543843 A JP S5543843A
Authority
JP
Japan
Prior art keywords
baking
disposition
targets
pattern
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11652578A
Other languages
Japanese (ja)
Inventor
Yasushi Asami
Yoshimitsu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11652578A priority Critical patent/JPS5543843A/en
Publication of JPS5543843A publication Critical patent/JPS5543843A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE: To improve a precision of relative position with a pattern on an element and also to improve a precision of baking with detecting targets by carrying out baking with a bifacial detecting target at a mask manufacturing process.
CONSTITUTION: Symbols 5a' and 5b' indicate identical patterns, and after baking with the pattern 5a' set on a mask manufacturing device, it is transferred straight to a given position for baking targets left and right with the same pattern. Then, a scribe area is kept in the middle of 5a' according to a disposition of a detecting target. The drawing indicates a disposition and a combination of targets of more than one in the case of 8 pairs, representing the scribe area being secured at disposition in division on two chips.
COPYRIGHT: (C)1980,JPO&Japio
JP11652578A 1978-09-25 1978-09-25 Semiconductor wafer and exposure mask for process thereof Pending JPS5543843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11652578A JPS5543843A (en) 1978-09-25 1978-09-25 Semiconductor wafer and exposure mask for process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11652578A JPS5543843A (en) 1978-09-25 1978-09-25 Semiconductor wafer and exposure mask for process thereof

Publications (1)

Publication Number Publication Date
JPS5543843A true JPS5543843A (en) 1980-03-27

Family

ID=14689279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11652578A Pending JPS5543843A (en) 1978-09-25 1978-09-25 Semiconductor wafer and exposure mask for process thereof

Country Status (1)

Country Link
JP (1) JPS5543843A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0325731U (en) * 1989-07-24 1991-03-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0325731U (en) * 1989-07-24 1991-03-15

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