JPS554704A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS554704A JPS554704A JP7521878A JP7521878A JPS554704A JP S554704 A JPS554704 A JP S554704A JP 7521878 A JP7521878 A JP 7521878A JP 7521878 A JP7521878 A JP 7521878A JP S554704 A JPS554704 A JP S554704A
- Authority
- JP
- Japan
- Prior art keywords
- line
- delay circuit
- trq6
- constitution
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 101150110971 CIN7 gene Proteins 0.000 abstract 1
- 101100286980 Daucus carota INV2 gene Proteins 0.000 abstract 1
- 101150110298 INV1 gene Proteins 0.000 abstract 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 abstract 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 abstract 1
- 230000003111 delayed effect Effects 0.000 abstract 1
- 230000000630 rising effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Read Only Memory (AREA)
Abstract
PURPOSE:To make a read speed high by rising and breaking rapidly the level change on a digit line by using a delay circuit to delay the operation of a feedback transistor. CONSTITUTION:Output terminal t is connected to read common line L1, by which the output of a selected memory cell is led out, through transistor TRQ3. Meanwhile, line L1 is connected to inverter INV1, and the output side is connected to feedback TRQ6 through a delay circuit, for example, resistive delay circuit R. Then, line L1 is connected to TRQ6 through INV2. By this constitution, the operation of TRQ6 can be delayed by a fixed time by delay circuit 6 at a level inversion time of line L1, so that the level change on the digit line can be risen and broken rapidly. As a result, the read speed can be made high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7521878A JPS554704A (en) | 1978-06-21 | 1978-06-21 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7521878A JPS554704A (en) | 1978-06-21 | 1978-06-21 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS554704A true JPS554704A (en) | 1980-01-14 |
| JPS5760719B2 JPS5760719B2 (en) | 1982-12-21 |
Family
ID=13569848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7521878A Granted JPS554704A (en) | 1978-06-21 | 1978-06-21 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS554704A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61165339U (en) * | 1985-04-03 | 1986-10-14 |
-
1978
- 1978-06-21 JP JP7521878A patent/JPS554704A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61165339U (en) * | 1985-04-03 | 1986-10-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5760719B2 (en) | 1982-12-21 |
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