JPS5562585A - Bubble memory tester - Google Patents

Bubble memory tester

Info

Publication number
JPS5562585A
JPS5562585A JP13371278A JP13371278A JPS5562585A JP S5562585 A JPS5562585 A JP S5562585A JP 13371278 A JP13371278 A JP 13371278A JP 13371278 A JP13371278 A JP 13371278A JP S5562585 A JPS5562585 A JP S5562585A
Authority
JP
Japan
Prior art keywords
address
pulse
counter
designates
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13371278A
Other languages
Japanese (ja)
Inventor
Koji Oba
Ryuji Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13371278A priority Critical patent/JPS5562585A/en
Publication of JPS5562585A publication Critical patent/JPS5562585A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the constitution of a tester considerably by causing a micro computer to execute functions of a counter, a coincidence circuit and a register.
CONSTITUTION: Micro computer (μCON) 1 designates a test address and waits till this address agrees with contents of minor loop counter 2. When they agree with each other, micro computer 1 detects the coincidence signal to give transfer pulse output information to pulse controller circuit 3 and outputs transfer-out signal 4, and simultaneously, designates an address from which the read pulse and the write pulse start for read and write respectively and waits till this address agrees with contents of counter 2. When detecting the coincidence signal, μCON1 indicates the output of each pulse to circuit 3 and designates the end address of pulses and waits till the address agrees with contents of counter 2. After that, similar operations are repeated, and at the end of pulses, a transfer pulse is outputted to complete the operation for one address.
COPYRIGHT: (C)1980,JPO&Japio
JP13371278A 1978-11-01 1978-11-01 Bubble memory tester Pending JPS5562585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13371278A JPS5562585A (en) 1978-11-01 1978-11-01 Bubble memory tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13371278A JPS5562585A (en) 1978-11-01 1978-11-01 Bubble memory tester

Publications (1)

Publication Number Publication Date
JPS5562585A true JPS5562585A (en) 1980-05-12

Family

ID=15111125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13371278A Pending JPS5562585A (en) 1978-11-01 1978-11-01 Bubble memory tester

Country Status (1)

Country Link
JP (1) JPS5562585A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5352373A (en) * 1976-10-25 1978-05-12 Agency Of Ind Science & Technol Automatic insepctor of shift register type memory chips of major-minor loop system
JPS53116749A (en) * 1977-03-22 1978-10-12 Bendix Corp Electronic circuit tester

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5352373A (en) * 1976-10-25 1978-05-12 Agency Of Ind Science & Technol Automatic insepctor of shift register type memory chips of major-minor loop system
JPS53116749A (en) * 1977-03-22 1978-10-12 Bendix Corp Electronic circuit tester

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