JPS5577228A - Flip-flop circuit - Google Patents

Flip-flop circuit

Info

Publication number
JPS5577228A
JPS5577228A JP15075078A JP15075078A JPS5577228A JP S5577228 A JPS5577228 A JP S5577228A JP 15075078 A JP15075078 A JP 15075078A JP 15075078 A JP15075078 A JP 15075078A JP S5577228 A JPS5577228 A JP S5577228A
Authority
JP
Japan
Prior art keywords
gates
circuit
signals
nand
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15075078A
Other languages
Japanese (ja)
Other versions
JPS625375B2 (en
Inventor
Osamu Oba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15075078A priority Critical patent/JPS5577228A/en
Publication of JPS5577228A publication Critical patent/JPS5577228A/en
Publication of JPS625375B2 publication Critical patent/JPS625375B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To reduce the number of elements and power consumption by reducing gates in number by constituting FF by standardized gates, and also to simplify circuit integration by making the circuit constitution symmetric. CONSTITUTION:Signals of data input terminals 8 and 9 are inputted to elements constituting NAND gates 1 and 2, and clocks from input terminal 10 are supplied to elements of those gates 1 and 2 after being inverted by turn by inverter 7; and outputs of NAND gates 3 and 4, and 5 and 6 are led to gates 1 and 2, where those input signals are combined. Then, signals of preset terminal 13 and clear terminal 14 are supplied to inputs of gates 1, 2, 3, and 4, and 5 and 6 and while gates 3 and 4 constitute a 1st latch circuit, gates 5 and 6 constitute a 2nd latch circuit; and outputs of gates 5 and 6 are connected to output terminals 11 and 12. Respective gates 1, 2, 3, and 4, and 5 and 6 of this circuit are composed of a NAND circuit or NOR circuit.
JP15075078A 1978-12-05 1978-12-05 Flip-flop circuit Granted JPS5577228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15075078A JPS5577228A (en) 1978-12-05 1978-12-05 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15075078A JPS5577228A (en) 1978-12-05 1978-12-05 Flip-flop circuit

Publications (2)

Publication Number Publication Date
JPS5577228A true JPS5577228A (en) 1980-06-10
JPS625375B2 JPS625375B2 (en) 1987-02-04

Family

ID=15503592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15075078A Granted JPS5577228A (en) 1978-12-05 1978-12-05 Flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS5577228A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029967U (en) * 1988-06-30 1990-01-23

Also Published As

Publication number Publication date
JPS625375B2 (en) 1987-02-04

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