JPS5586144A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5586144A
JPS5586144A JP15853878A JP15853878A JPS5586144A JP S5586144 A JPS5586144 A JP S5586144A JP 15853878 A JP15853878 A JP 15853878A JP 15853878 A JP15853878 A JP 15853878A JP S5586144 A JPS5586144 A JP S5586144A
Authority
JP
Japan
Prior art keywords
substrate
concave part
metal layer
base
bottom face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15853878A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yoshimoto
Katsuyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP15853878A priority Critical patent/JPS5586144A/en
Publication of JPS5586144A publication Critical patent/JPS5586144A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To suppress the fluctuation of substrate potential and stabilize operations in an IC substrate by connecting a smoothing capacitor between a part on the substrate potential and the earth lead of the IC substrate. CONSTITUTION:Over a ceramic base 22 with a concave part on its surface, a metal layer 29 is coated from the concave part via one of the convex parts and a side face to the center of the bottom face, and also from the other convex part via a side face to the center of the bottom face, a metal layer 30 is coated, and the metal layers 29 and 30 are insulated with each other on the bottom face by an insulating layer 31. Next, in the concave part of the base 22, an IC substrate 21 is fixed, and electrodes provided on it are connected with a lead 26 and an earth lead 27 penetrating seal glass 25 provided on the convex parts by bonding wires 28. next, on the base 22, a ceramic cap 23 with a concave part on the lower face is placed via the glass 25 and a space 24 is formed over the substrate 21. By so doing, a capacitor Cext is formed between the end 29B of the metal layer 29 and the end 30B of the layer 30, and the fluctuation of the substrate potential is reduced.
JP15853878A 1978-12-25 1978-12-25 Semiconductor device Pending JPS5586144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15853878A JPS5586144A (en) 1978-12-25 1978-12-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15853878A JPS5586144A (en) 1978-12-25 1978-12-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5586144A true JPS5586144A (en) 1980-06-28

Family

ID=15673894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15853878A Pending JPS5586144A (en) 1978-12-25 1978-12-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5586144A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646126A (en) * 1983-10-07 1987-02-24 Kabushiki Kaisha Toshiba Semiconductor device
US4675717A (en) * 1984-10-09 1987-06-23 American Telephone And Telegraph Company, At&T Bell Laboratories Water-scale-integrated assembly
US4796083A (en) * 1987-07-02 1989-01-03 Olin Corporation Semiconductor casing
US4949163A (en) * 1987-04-15 1990-08-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device particularly for high speed logic operations
US4953006A (en) * 1989-07-27 1990-08-28 Northern Telecom Limited Packaging method and package for edge-coupled optoelectronic device
US5043535A (en) * 1989-03-10 1991-08-27 Olin Corporation Hermetic cerglass and cermet electronic packages
US5134539A (en) * 1990-12-17 1992-07-28 Nchip, Inc. Multichip module having integral decoupling capacitor
US5214844A (en) * 1990-12-17 1993-06-01 Nchip, Inc. Method of assembling integrated circuits to a silicon board
US5254871A (en) * 1988-11-08 1993-10-19 Bull, S.A. Very large scale integrated circuit package, integrated circuit carrier and resultant interconnection board
US5274270A (en) * 1990-12-17 1993-12-28 Nchip, Inc. Multichip module having SiO2 insulating layer
US5666004A (en) * 1994-09-28 1997-09-09 Intel Corporation Use of tantalum oxide capacitor on ceramic co-fired technology
WO1998044687A1 (en) * 1997-03-31 1998-10-08 Hitachi, Ltd. Modem using capacitive insulating barrier, insulating coupler, and integrated circuit used in the modem

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646126A (en) * 1983-10-07 1987-02-24 Kabushiki Kaisha Toshiba Semiconductor device
US4675717A (en) * 1984-10-09 1987-06-23 American Telephone And Telegraph Company, At&T Bell Laboratories Water-scale-integrated assembly
US4949163A (en) * 1987-04-15 1990-08-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device particularly for high speed logic operations
US4796083A (en) * 1987-07-02 1989-01-03 Olin Corporation Semiconductor casing
US5254871A (en) * 1988-11-08 1993-10-19 Bull, S.A. Very large scale integrated circuit package, integrated circuit carrier and resultant interconnection board
US5043535A (en) * 1989-03-10 1991-08-27 Olin Corporation Hermetic cerglass and cermet electronic packages
US4953006A (en) * 1989-07-27 1990-08-28 Northern Telecom Limited Packaging method and package for edge-coupled optoelectronic device
US5134539A (en) * 1990-12-17 1992-07-28 Nchip, Inc. Multichip module having integral decoupling capacitor
US5214844A (en) * 1990-12-17 1993-06-01 Nchip, Inc. Method of assembling integrated circuits to a silicon board
US5274270A (en) * 1990-12-17 1993-12-28 Nchip, Inc. Multichip module having SiO2 insulating layer
US5666004A (en) * 1994-09-28 1997-09-09 Intel Corporation Use of tantalum oxide capacitor on ceramic co-fired technology
WO1998044687A1 (en) * 1997-03-31 1998-10-08 Hitachi, Ltd. Modem using capacitive insulating barrier, insulating coupler, and integrated circuit used in the modem

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