JPS5587450A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPS5587450A
JPS5587450A JP16151678A JP16151678A JPS5587450A JP S5587450 A JPS5587450 A JP S5587450A JP 16151678 A JP16151678 A JP 16151678A JP 16151678 A JP16151678 A JP 16151678A JP S5587450 A JPS5587450 A JP S5587450A
Authority
JP
Japan
Prior art keywords
resin
inlet
upper mould
mould
filled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16151678A
Other languages
Japanese (ja)
Other versions
JPS6046540B2 (en
Inventor
Yoshiharu Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP53161516A priority Critical patent/JPS6046540B2/en
Publication of JPS5587450A publication Critical patent/JPS5587450A/en
Publication of JPS6046540B2 publication Critical patent/JPS6046540B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To obtain a highly reliable device without problems like disconnection and to increase the productivity by a method wherein a resin is filled and moulded after having inserted an electronic component in a mould of circuit substrate.
CONSTITUTION: With the external outlet electrode looking downward, a semiconductor chip 2 is placed on a lower mould 11 which is provided with locating pins 10, the chip 2 being surrounded by the pins 10, on which an upper mould 12 is covered and then clamped. A resin A is filled through an inlet 13, which is formed on the upper mould 12, to form a buffer layer over the surface and side face of a chip 2. Then, the upper mould 12 is removed and the resin A solidified in the shape of the inlet 13 is removed. After that, another upper mould 15 is clamped similarly and a resin B is filled through this inlet 16 to make a circuit substrate 17 by surrounding a layer 14. Then, the upper mould 15 is removed to free the substrate 17 from the lower mould 11. After having removed the resin B remained in the shape of the inlet 16, the substrate 17 is turned around to match with the electrodes exposed herein resulting in the printing and formation of a wiring pattern 18.
COPYRIGHT: (C)1980,JPO&Japio
JP53161516A 1978-12-26 1978-12-26 Electronic device manufacturing method Expired JPS6046540B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53161516A JPS6046540B2 (en) 1978-12-26 1978-12-26 Electronic device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53161516A JPS6046540B2 (en) 1978-12-26 1978-12-26 Electronic device manufacturing method

Publications (2)

Publication Number Publication Date
JPS5587450A true JPS5587450A (en) 1980-07-02
JPS6046540B2 JPS6046540B2 (en) 1985-10-16

Family

ID=15736548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53161516A Expired JPS6046540B2 (en) 1978-12-26 1978-12-26 Electronic device manufacturing method

Country Status (1)

Country Link
JP (1) JPS6046540B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136641A (en) * 1986-11-28 1988-06-08 Toppan Printing Co Ltd Integrated circuit chip mount and mounting method for integrated circuit chip

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102898959B1 (en) * 2023-05-25 2025-12-10 인하대학교 산학협력단 A latent curing agent compound and an epoxy resin composition comprising the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136641A (en) * 1986-11-28 1988-06-08 Toppan Printing Co Ltd Integrated circuit chip mount and mounting method for integrated circuit chip

Also Published As

Publication number Publication date
JPS6046540B2 (en) 1985-10-16

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