JPS5587491A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS5587491A
JPS5587491A JP16042978A JP16042978A JPS5587491A JP S5587491 A JPS5587491 A JP S5587491A JP 16042978 A JP16042978 A JP 16042978A JP 16042978 A JP16042978 A JP 16042978A JP S5587491 A JPS5587491 A JP S5587491A
Authority
JP
Japan
Prior art keywords
film
gate
mask
etched
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16042978A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16042978A priority Critical patent/JPS5587491A/en
Publication of JPS5587491A publication Critical patent/JPS5587491A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve the integration level by means of an auxiliary control gate in a gate insulation film between a floating gate and the substrate. CONSTITUTION:An impurity adding poly Si film 24 is selectively formed on a gate oxide form 23 of a p-type Si substrate. Then, with the film 24 as mask, the film 23 is etched away. Successively, an SiO2 film 25, an impurity adding poly Si film 26, an SiO2 film 27 and an impurity adding poly Si film 28 are laminated. With a resist mask 29 applied, the films 28-24 are etched aways, and after the removal of the resist 29, the SiO2 film 23 is etched with the poly Si film 28 as mask. Then, an n<+>-type layers 30 and 31 are provided. With such an arrangement, it is possible to obtaine a non-voratile memory device maintaining the characteristics at a level exceeding that of the conventional ones, without extending the float gate on the field region.
JP16042978A 1978-12-25 1978-12-25 Non-volatile semiconductor memory device Pending JPS5587491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16042978A JPS5587491A (en) 1978-12-25 1978-12-25 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16042978A JPS5587491A (en) 1978-12-25 1978-12-25 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5587491A true JPS5587491A (en) 1980-07-02

Family

ID=15714731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16042978A Pending JPS5587491A (en) 1978-12-25 1978-12-25 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5587491A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4989053A (en) * 1989-03-27 1991-01-29 Shelton Everett K Nonvolatile process compatible with a digital and analog double level metal MOS process
US5394360A (en) * 1990-07-06 1995-02-28 Sharp Kabushiki Kaisha Non-volatile large capacity high speed memory with electron injection from a source into a floating gate
US6057575A (en) * 1996-03-18 2000-05-02 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
US6335553B1 (en) * 1997-05-26 2002-01-01 Lg Semicon Co., Ltd. Nonvolatile semiconductor memory and method of fabrication
US6954381B2 (en) 1992-01-14 2005-10-11 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4989053A (en) * 1989-03-27 1991-01-29 Shelton Everett K Nonvolatile process compatible with a digital and analog double level metal MOS process
US5394360A (en) * 1990-07-06 1995-02-28 Sharp Kabushiki Kaisha Non-volatile large capacity high speed memory with electron injection from a source into a floating gate
US6954381B2 (en) 1992-01-14 2005-10-11 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6057575A (en) * 1996-03-18 2000-05-02 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
US6335553B1 (en) * 1997-05-26 2002-01-01 Lg Semicon Co., Ltd. Nonvolatile semiconductor memory and method of fabrication

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