JPS6437876A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6437876A
JPS6437876A JP62193978A JP19397887A JPS6437876A JP S6437876 A JPS6437876 A JP S6437876A JP 62193978 A JP62193978 A JP 62193978A JP 19397887 A JP19397887 A JP 19397887A JP S6437876 A JPS6437876 A JP S6437876A
Authority
JP
Japan
Prior art keywords
film
oxide film
gate
floating gate
tunnel oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62193978A
Other languages
Japanese (ja)
Inventor
Fumihiko Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62193978A priority Critical patent/JPS6437876A/en
Publication of JPS6437876A publication Critical patent/JPS6437876A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To increase the quantity of passing electricity resulting in the breakdown of a tunnel oxide film largely by composing a floating gate of amorphous Si when the floating gate insulated by the tunnel oxide film and all inter-layer insulating film extending over a source region and a drain region and a control gate are formed. CONSTITUTION:n<+> type source region 4 and drain region 5 surrounded by a thick field oxide film 2 are shaped to the surface layer section of a p-type Si substrate 1, and a thin gate oxide film 6 is applied onto the exposed surfaces of the regions 4 and 5 and the substrate 1. One part of the film 6 positioned onto the region 5 is removed through dry etching, and oxidized again and changed into a thin tunnel oxide film 7. A control gate 10 through a floating gate 8 and an inter-layer insulating film 9 is formed onto the film 6 including the tunnel oxide film 7, and these gates and film are surrounded by an SiO2 layer 11, but amorphous Si is used without employing polycrystalline Si as the floating gate 8 at that time. Accordingly, the state of the interface between the gate 8 and the film 7 is improved.
JP62193978A 1987-08-03 1987-08-03 Manufacture of semiconductor device Pending JPS6437876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62193978A JPS6437876A (en) 1987-08-03 1987-08-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62193978A JPS6437876A (en) 1987-08-03 1987-08-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6437876A true JPS6437876A (en) 1989-02-08

Family

ID=16316941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62193978A Pending JPS6437876A (en) 1987-08-03 1987-08-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6437876A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07240478A (en) * 1994-02-23 1995-09-12 Lg Semicon Co Ltd Method for manufacturing non-volatile semiconductor memory device
US5532070A (en) * 1992-06-02 1996-07-02 Ibiden Co., Ltd. Solder-precoated conductor circuit substrate and method of producing the same
JP2013172097A (en) * 2012-02-22 2013-09-02 Seiko Instruments Inc Semiconductor nonvolatile memory device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182267A (en) * 1985-02-08 1986-08-14 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device
JPS62145872A (en) * 1985-12-17 1987-06-29 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Improved MOS integrated circuit structure and method of construction thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182267A (en) * 1985-02-08 1986-08-14 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device
JPS62145872A (en) * 1985-12-17 1987-06-29 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Improved MOS integrated circuit structure and method of construction thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532070A (en) * 1992-06-02 1996-07-02 Ibiden Co., Ltd. Solder-precoated conductor circuit substrate and method of producing the same
JPH07240478A (en) * 1994-02-23 1995-09-12 Lg Semicon Co Ltd Method for manufacturing non-volatile semiconductor memory device
JP2013172097A (en) * 2012-02-22 2013-09-02 Seiko Instruments Inc Semiconductor nonvolatile memory device

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