JPS5649570A - Semiconductor memory and its manufacturing process - Google Patents

Semiconductor memory and its manufacturing process

Info

Publication number
JPS5649570A
JPS5649570A JP12412779A JP12412779A JPS5649570A JP S5649570 A JPS5649570 A JP S5649570A JP 12412779 A JP12412779 A JP 12412779A JP 12412779 A JP12412779 A JP 12412779A JP S5649570 A JPS5649570 A JP S5649570A
Authority
JP
Japan
Prior art keywords
layer
gate
polysilicon
film
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12412779A
Other languages
Japanese (ja)
Inventor
Kazuhiro Komori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12412779A priority Critical patent/JPS5649570A/en
Priority to DE19803036452 priority patent/DE3036452A1/en
Publication of JPS5649570A publication Critical patent/JPS5649570A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To get a small-sizedmemory unit with a good holding characteristic by piling Si3N4 or polysilicon film on SiO2 film. CONSTITUTION:Field film oxide 11, P<+> channel stopper 11A are formed on a P type Si substrate 10, a polysilicon floating gate 13 layer is made on gate film oxide 12 to be covered with film oxide 14 further laminated with a polysilicon control gate 15 layer to form gate electrodes 15, 13 by single photographic etching. Next N<+> source, drain 16, 17 and a source taking out layer 16' are formed through ion injection and self-matching to make polysilicon 15, 13 conductive. Nextby selectively making an opening Al bit wiring 21 connecting with an N<+> layer 17 is made. By piling Si3N4 19 with the damp-proof properties on SiO2 18 covering memory cells the gate 13 has an extremely good holding characteristic and the single photographic etching makes it possible to reduce the cell size.
JP12412779A 1979-09-28 1979-09-28 Semiconductor memory and its manufacturing process Pending JPS5649570A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP12412779A JPS5649570A (en) 1979-09-28 1979-09-28 Semiconductor memory and its manufacturing process
DE19803036452 DE3036452A1 (en) 1979-09-28 1980-09-26 Electronically programmable read-only memory device - with increased integration density and data retaining property

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12412779A JPS5649570A (en) 1979-09-28 1979-09-28 Semiconductor memory and its manufacturing process

Publications (1)

Publication Number Publication Date
JPS5649570A true JPS5649570A (en) 1981-05-06

Family

ID=14877588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12412779A Pending JPS5649570A (en) 1979-09-28 1979-09-28 Semiconductor memory and its manufacturing process

Country Status (2)

Country Link
JP (1) JPS5649570A (en)
DE (1) DE3036452A1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175749U (en) * 1982-05-19 1983-11-24 アイカ工業株式会社 Melamine resin decorative board pasted top plate
JPS5920A (en) * 1982-06-21 1984-01-05 藤沢　良文 Reinforcing of l-shaped assembling part of wood product
JPS59111558U (en) * 1983-01-19 1984-07-27 株式会社岡村製作所 Wooden top plate for sink
US5153144A (en) * 1988-05-10 1992-10-06 Hitachi, Ltd. Method of making tunnel EEPROM
US5208175A (en) * 1990-12-21 1993-05-04 Samsung Electronics Co., Ltd. Method of making a nonvolatile semiconductor memory device
US5445980A (en) * 1988-05-10 1995-08-29 Hitachi, Ltd. Method of making a semiconductor memory device
US6284638B1 (en) * 1992-12-08 2001-09-04 Fujitsu Limited Manufacturing method of a semiconductor device
US6921964B2 (en) 2001-02-08 2005-07-26 Seiko Epson Corporation Semiconductor device having a non-volatile memory transistor formed on a semiconductor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3739667C2 (en) * 1987-11-24 1996-10-17 Dynamit Nobel Ag Reusable explosive device
JPH03232231A (en) * 1990-02-08 1991-10-16 Toshiba Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5457972A (en) * 1977-09-27 1979-05-10 Siemens Ag Erasable nonnvolatile memory and method of driving same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5457972A (en) * 1977-09-27 1979-05-10 Siemens Ag Erasable nonnvolatile memory and method of driving same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175749U (en) * 1982-05-19 1983-11-24 アイカ工業株式会社 Melamine resin decorative board pasted top plate
JPS5920A (en) * 1982-06-21 1984-01-05 藤沢　良文 Reinforcing of l-shaped assembling part of wood product
JPS59111558U (en) * 1983-01-19 1984-07-27 株式会社岡村製作所 Wooden top plate for sink
US5153144A (en) * 1988-05-10 1992-10-06 Hitachi, Ltd. Method of making tunnel EEPROM
US5445980A (en) * 1988-05-10 1995-08-29 Hitachi, Ltd. Method of making a semiconductor memory device
USRE37959E1 (en) 1988-05-10 2003-01-07 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US5208175A (en) * 1990-12-21 1993-05-04 Samsung Electronics Co., Ltd. Method of making a nonvolatile semiconductor memory device
US6284638B1 (en) * 1992-12-08 2001-09-04 Fujitsu Limited Manufacturing method of a semiconductor device
US6921964B2 (en) 2001-02-08 2005-07-26 Seiko Epson Corporation Semiconductor device having a non-volatile memory transistor formed on a semiconductor

Also Published As

Publication number Publication date
DE3036452A1 (en) 1981-04-09

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