JPS55913A - Divider circuit - Google Patents

Divider circuit

Info

Publication number
JPS55913A
JPS55913A JP7284078A JP7284078A JPS55913A JP S55913 A JPS55913 A JP S55913A JP 7284078 A JP7284078 A JP 7284078A JP 7284078 A JP7284078 A JP 7284078A JP S55913 A JPS55913 A JP S55913A
Authority
JP
Japan
Prior art keywords
gain variable
division
differential amplifiers
circuit
balancing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7284078A
Other languages
Japanese (ja)
Other versions
JPS6342311B2 (en
Inventor
Masaru Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7284078A priority Critical patent/JPS55913A/en
Priority to US06/049,084 priority patent/US4353000A/en
Publication of JPS55913A publication Critical patent/JPS55913A/en
Publication of JPS6342311B2 publication Critical patent/JPS6342311B2/ja
Granted legal-status Critical Current

Links

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To realize precise division operation by canceling the fixed components of signals A and B by using as a gain variable circuit a double balancing circuit with differential amplifiers combined. CONSTITUTION:Division signal A from terminal 1 is inputted to the 1st and 3rd gain variable circuits Q1 and Q2, and Q3 and Q4, double balancing circuit obtained by combining differential amplifiers Q5 and Q6, and the outputs of the 1st gain variable circuits Q1 and Q2 are fed back as control voltage V to hold automatically the output P(V).A nearly constant. On the other hand, the 2nd gain variable circuits Q7 and Q8 whose gains are expressed by P(V) are applied with the same control voltage while divided signal B is supplied from terminal 2, so that a signal equivalent to the division result will appear at the output. Since the double balancing circuit with differential amplifiers combined is used as this gain variable circuit, division is so perfomed that fixed components such as a direct-current bias component will be canceled.
JP7284078A 1978-06-16 1978-06-16 Divider circuit Granted JPS55913A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7284078A JPS55913A (en) 1978-06-16 1978-06-16 Divider circuit
US06/049,084 US4353000A (en) 1978-06-16 1979-06-18 Divider circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7284078A JPS55913A (en) 1978-06-16 1978-06-16 Divider circuit

Publications (2)

Publication Number Publication Date
JPS55913A true JPS55913A (en) 1980-01-07
JPS6342311B2 JPS6342311B2 (en) 1988-08-23

Family

ID=13500989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7284078A Granted JPS55913A (en) 1978-06-16 1978-06-16 Divider circuit

Country Status (1)

Country Link
JP (1) JPS55913A (en)

Also Published As

Publication number Publication date
JPS6342311B2 (en) 1988-08-23

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