JPS5592950A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS5592950A
JPS5592950A JP16579178A JP16579178A JPS5592950A JP S5592950 A JPS5592950 A JP S5592950A JP 16579178 A JP16579178 A JP 16579178A JP 16579178 A JP16579178 A JP 16579178A JP S5592950 A JPS5592950 A JP S5592950A
Authority
JP
Japan
Prior art keywords
interruption
decision part
address
psw
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16579178A
Other languages
Japanese (ja)
Inventor
Shigemitsu Ashizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP16579178A priority Critical patent/JPS5592950A/en
Publication of JPS5592950A publication Critical patent/JPS5592950A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the interruption processing time and to reduce memory capacity by determining addresses of a reference information storage area during an interruption process by an interruption acceptance method and then by performing a pre- process through hardware.
CONSTITUTION: As an interruption acceptance method, interruption vector address decision part 1 and reference table address decision part 2 are provided. Once an interruption is accepted, decision part 1 obtains interruption vector address IVA by interruption factor code INT.FCT.CD and new processor status word PSW in CPU and the content of program counter PC are extracted from interruption vector area VA and set in a PSW register and register area REGA. Old values of PSW and PC are stored in stack area STKA. Decision part 2 determines reference table address RTA by interruption unit code INT.DC.CD and stores it in REGA. At this time, the old value of address register XR is transferred to STKA. Therefore, RTA to be referred to is stored at the time of an interruption process, so that the processing time will be shortened.
COPYRIGHT: (C)1980,JPO&Japio
JP16579178A 1978-12-30 1978-12-30 Interruption control system Pending JPS5592950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16579178A JPS5592950A (en) 1978-12-30 1978-12-30 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16579178A JPS5592950A (en) 1978-12-30 1978-12-30 Interruption control system

Publications (1)

Publication Number Publication Date
JPS5592950A true JPS5592950A (en) 1980-07-14

Family

ID=15819054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16579178A Pending JPS5592950A (en) 1978-12-30 1978-12-30 Interruption control system

Country Status (1)

Country Link
JP (1) JPS5592950A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870355A (en) * 1981-10-21 1983-04-26 Fuji Electric Co Ltd Microprogram controlling system
JPS5880742A (en) * 1981-11-09 1983-05-14 Fuji Electric Co Ltd Controlling system of microprogram
JPH02144630A (en) * 1988-11-25 1990-06-04 Nec Corp Data processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870355A (en) * 1981-10-21 1983-04-26 Fuji Electric Co Ltd Microprogram controlling system
JPS5880742A (en) * 1981-11-09 1983-05-14 Fuji Electric Co Ltd Controlling system of microprogram
JPH02144630A (en) * 1988-11-25 1990-06-04 Nec Corp Data processor

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