JPS5599768A - Semicondcutor device - Google Patents

Semicondcutor device

Info

Publication number
JPS5599768A
JPS5599768A JP796779A JP796779A JPS5599768A JP S5599768 A JPS5599768 A JP S5599768A JP 796779 A JP796779 A JP 796779A JP 796779 A JP796779 A JP 796779A JP S5599768 A JPS5599768 A JP S5599768A
Authority
JP
Japan
Prior art keywords
layer
contact
polycrystalline
wiring
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP796779A
Other languages
Japanese (ja)
Other versions
JPS621258B2 (en
Inventor
Taiichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP796779A priority Critical patent/JPS5599768A/en
Publication of JPS5599768A publication Critical patent/JPS5599768A/en
Publication of JPS621258B2 publication Critical patent/JPS621258B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To prevent damage to the contact due to the impression of a large current and obtain a high-reliability contact structure by the method wherein almost all the part surrounding the electrode opening has a polycrystalline Si layer, a part of the Si layer and a part of the impurity region make contact with each other, and the wiring electrode comes in contact with a part of the Si region and a part of the impurity region.
CONSTITUTION: Impurity diffused region 2 is formed on semiconductor substrate 1. By removing insulating film 3, a contact hole is made, and polycrystalline Si layer 6, which is a conducting layer, is grown on the entire surface. On top of this, Al layer 4 is evaporated, and a wiring pattern is formed. Si layer 6, except for the part below the Al wiring layer, is removed. Consequently, since the polycrystalline Si layer is provided in the part surrounding the contact and the part below the wiring layer, the occurrence of alloy spike in the part surrounding the contact is checked.
COPYRIGHT: (C)1980,JPO&Japio
JP796779A 1979-01-25 1979-01-25 Semicondcutor device Granted JPS5599768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP796779A JPS5599768A (en) 1979-01-25 1979-01-25 Semicondcutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP796779A JPS5599768A (en) 1979-01-25 1979-01-25 Semicondcutor device

Publications (2)

Publication Number Publication Date
JPS5599768A true JPS5599768A (en) 1980-07-30
JPS621258B2 JPS621258B2 (en) 1987-01-12

Family

ID=11680226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP796779A Granted JPS5599768A (en) 1979-01-25 1979-01-25 Semicondcutor device

Country Status (1)

Country Link
JP (1) JPS5599768A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58210667A (en) * 1982-06-01 1983-12-07 Toshiba Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58210667A (en) * 1982-06-01 1983-12-07 Toshiba Corp Semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
JPS621258B2 (en) 1987-01-12

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