JPS5610963A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5610963A JPS5610963A JP8761579A JP8761579A JPS5610963A JP S5610963 A JPS5610963 A JP S5610963A JP 8761579 A JP8761579 A JP 8761579A JP 8761579 A JP8761579 A JP 8761579A JP S5610963 A JPS5610963 A JP S5610963A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- emitter
- layer
- base
- perpendicularly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
Landscapes
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
PURPOSE:To obtain a bipolar transistor BPT with a gate for large power by forming the gate region in stripe state and intersecting an emitter layer perpendicularly with the gate region to increase the width of the emitter layer regardless of the interval between the gate regions. CONSTITUTION:Striped emitter layers 3a are arranged perpendicularly with gate regions 4, and a base electrode 6a is provided on a base layer 2 between the emitter electrodes 5a and the emitter layers 3a perpendicularly with the gate regions. In this case the interval 2a between the gate regions is determined as prescribed depending upon an angle of the junction plane between the gate layer 4 and the collector layer 1 from a normal line at predetermined position, impurity densities of the collector and the base, and the width of the base, and the like. Since the emitter 3a is intersected perpendicularly with the gate 4 even if the collector 1 interposed between the gates 4 is contrived to be pinched off prior to the punch through of the base 2, the width LE of the emitter layer can be increased irrespective of the interval 2a. Accordingly, it can obtain a bipolar transistor BPT with a gate for large power.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8761579A JPS5610963A (en) | 1979-07-09 | 1979-07-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8761579A JPS5610963A (en) | 1979-07-09 | 1979-07-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5610963A true JPS5610963A (en) | 1981-02-03 |
| JPS6331107B2 JPS6331107B2 (en) | 1988-06-22 |
Family
ID=13919875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8761579A Granted JPS5610963A (en) | 1979-07-09 | 1979-07-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5610963A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04136500U (en) * | 1991-06-07 | 1992-12-18 | 川崎重工業株式会社 | dust removal device |
-
1979
- 1979-07-09 JP JP8761579A patent/JPS5610963A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04136500U (en) * | 1991-06-07 | 1992-12-18 | 川崎重工業株式会社 | dust removal device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6331107B2 (en) | 1988-06-22 |
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