JPS5646531A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5646531A JPS5646531A JP12298779A JP12298779A JPS5646531A JP S5646531 A JPS5646531 A JP S5646531A JP 12298779 A JP12298779 A JP 12298779A JP 12298779 A JP12298779 A JP 12298779A JP S5646531 A JPS5646531 A JP S5646531A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- masks
- film
- plasma
- resist mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
PURPOSE:To form a microminiature semiconductor device by ethcing with CF4 plasma or implanting ions and then superimposing again a resist mask through a thin film of Al or SiO2 having good drape with a resist on the surface of a substrate where a resist pattern is not removed. CONSTITUTION:An N type layer is formed on a P type Si substrate, an Si3N4 is superimposed on the SiO2 film, resist masks 51, 52 are covered thereon, are etched with CF4 plasma, and Si3N4 masks 41, 42 are formed. CF4 plasma is further irradiated to the surfaces 55, 56 of the resist masks 51, 52 and the latters are transformed into heat resistant modified layers. Then, a CVD SiO2 6 is covered thereon, the second resist mask 72 is formed thereon, B ions are implanted thereon, and a channel stopper 8 is formed thereon. The resist mask 6 and the film 3 are subsequently removed, and a field oxide film 9 is formed with the masks 41, 42. Successively, the masks 41, 42 and the film 3 are removed, and a C-MOS device is then completed by an ordinary process. Since the modified heat resistant resist mask does not deform at high temperature at the time of irradiating the plasma but may easily form a metal or insulating film according to this configuration, a microminiature pattern can be formed, and a high density IC can consequently be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12298779A JPS5646531A (en) | 1979-09-25 | 1979-09-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12298779A JPS5646531A (en) | 1979-09-25 | 1979-09-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5646531A true JPS5646531A (en) | 1981-04-27 |
Family
ID=14849482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12298779A Pending JPS5646531A (en) | 1979-09-25 | 1979-09-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5646531A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8409457B2 (en) | 2008-08-29 | 2013-04-02 | Micron Technology, Inc. | Methods of forming a photoresist-comprising pattern on a substrate |
| US9653315B2 (en) | 2008-12-04 | 2017-05-16 | Micron Technology, Inc. | Methods of fabricating substrates |
| US9761457B2 (en) | 2006-07-10 | 2017-09-12 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
-
1979
- 1979-09-25 JP JP12298779A patent/JPS5646531A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9761457B2 (en) | 2006-07-10 | 2017-09-12 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US10096483B2 (en) | 2006-07-10 | 2018-10-09 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US10607844B2 (en) | 2006-07-10 | 2020-03-31 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US11335563B2 (en) | 2006-07-10 | 2022-05-17 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US11935756B2 (en) | 2006-07-10 | 2024-03-19 | Lodestar Licensing Group Llc | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US12463044B2 (en) | 2006-07-10 | 2025-11-04 | Lodestar Licensing Group Llc | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
| US8409457B2 (en) | 2008-08-29 | 2013-04-02 | Micron Technology, Inc. | Methods of forming a photoresist-comprising pattern on a substrate |
| US9653315B2 (en) | 2008-12-04 | 2017-05-16 | Micron Technology, Inc. | Methods of fabricating substrates |
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