JPS5656666A - Mos integrated circuit device and preparation thereof - Google Patents

Mos integrated circuit device and preparation thereof

Info

Publication number
JPS5656666A
JPS5656666A JP13389979A JP13389979A JPS5656666A JP S5656666 A JPS5656666 A JP S5656666A JP 13389979 A JP13389979 A JP 13389979A JP 13389979 A JP13389979 A JP 13389979A JP S5656666 A JPS5656666 A JP S5656666A
Authority
JP
Japan
Prior art keywords
gate
fet
threshold voltage
width
fets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13389979A
Other languages
Japanese (ja)
Inventor
Kiyoshi Morimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13389979A priority Critical patent/JPS5656666A/en
Publication of JPS5656666A publication Critical patent/JPS5656666A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a leak current throughout the device by a method wherein the threshold voltage of MOSFETs is leveled approximately and thereby the tailing properties which the FET with a large gate width usually has are made excellent in the MOSIC wherein the FETs having large or small gate width respectively are mixed. CONSTITUTION:A source region 1 having source electrodes 4 on both sides of a gate region 3 provided with a gate electrode 6 and a drain region 2 having a drain electrode 5 are arranged to compose an FET. Next, two FETs are formed on the same semiconductor substrate to compose an MOSIC. On the occasion, when there is any difference in the gate width W of the FETs, the tailing phenomenon wherein the drain current changes logarithmically in relation to the gate voltage at the threshold voltage or below is caused in the FET which has a large width. In order to eliminate this phenomenon, an ion is injected into the FET having a large W/L ratio, where L is the length of the gate and W is the width of the gate, so as to raise the threshold voltage. Thus, the threshold voltage of two FET is leveled approximately, whereby the increase in the leak current is prevented.
JP13389979A 1979-10-13 1979-10-13 Mos integrated circuit device and preparation thereof Pending JPS5656666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13389979A JPS5656666A (en) 1979-10-13 1979-10-13 Mos integrated circuit device and preparation thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13389979A JPS5656666A (en) 1979-10-13 1979-10-13 Mos integrated circuit device and preparation thereof

Publications (1)

Publication Number Publication Date
JPS5656666A true JPS5656666A (en) 1981-05-18

Family

ID=15115700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13389979A Pending JPS5656666A (en) 1979-10-13 1979-10-13 Mos integrated circuit device and preparation thereof

Country Status (1)

Country Link
JP (1) JPS5656666A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4989061A (en) * 1986-09-05 1991-01-29 General Electric Company Radiation hard memory cell structure with drain shielding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4989061A (en) * 1986-09-05 1991-01-29 General Electric Company Radiation hard memory cell structure with drain shielding

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