JPS5657127A - Digital input/output circuit - Google Patents

Digital input/output circuit

Info

Publication number
JPS5657127A
JPS5657127A JP13272079A JP13272079A JPS5657127A JP S5657127 A JPS5657127 A JP S5657127A JP 13272079 A JP13272079 A JP 13272079A JP 13272079 A JP13272079 A JP 13272079A JP S5657127 A JPS5657127 A JP S5657127A
Authority
JP
Japan
Prior art keywords
level
fetq
resistance
sel
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13272079A
Other languages
Japanese (ja)
Inventor
Ryoji Gamo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13272079A priority Critical patent/JPS5657127A/en
Publication of JPS5657127A publication Critical patent/JPS5657127A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE: To make it possible to reduce considerably the circuit current consumption in output operation, by disconnecting the pull-up resistance for input processing only at the input operation in respect to the terminal having the input/output function.
CONSTITUTION: During the output operation, select signal inversion SEL is high- level, and p-channel type FETQ2 is turned off. Consequently, pull-up resistance Rp is not the load of output buffer B1. Meanwhile, during the input operation to read the state of rotary switch RSW, buffer B1 is not enabled but is in high-impedance state. Signal inversion SEL is low-level, and signal SEL is high-level, and FETs Q1 and Q2 are turned on. Consequently, only the data line connected to movable contact VS of switch RSW becomes low-level due to turning-on of FETQ1, and other data lines become high-level due to turning-on of FETQ2 and resistance Rp. At this time, the current flowed to the circuit is only the current flowed through contact VS.
COPYRIGHT: (C)1981,JPO&Japio
JP13272079A 1979-10-15 1979-10-15 Digital input/output circuit Pending JPS5657127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13272079A JPS5657127A (en) 1979-10-15 1979-10-15 Digital input/output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13272079A JPS5657127A (en) 1979-10-15 1979-10-15 Digital input/output circuit

Publications (1)

Publication Number Publication Date
JPS5657127A true JPS5657127A (en) 1981-05-19

Family

ID=15087993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13272079A Pending JPS5657127A (en) 1979-10-15 1979-10-15 Digital input/output circuit

Country Status (1)

Country Link
JP (1) JPS5657127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4596984A (en) * 1982-09-17 1986-06-24 Mitsubishi Denki Kabushiki Kaisha Digital data input circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4596984A (en) * 1982-09-17 1986-06-24 Mitsubishi Denki Kabushiki Kaisha Digital data input circuit

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