JPS5671950A - Manufacture of integrated semiconductor circuit - Google Patents

Manufacture of integrated semiconductor circuit

Info

Publication number
JPS5671950A
JPS5671950A JP14890379A JP14890379A JPS5671950A JP S5671950 A JPS5671950 A JP S5671950A JP 14890379 A JP14890379 A JP 14890379A JP 14890379 A JP14890379 A JP 14890379A JP S5671950 A JPS5671950 A JP S5671950A
Authority
JP
Japan
Prior art keywords
film
groove
layer
substrate
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14890379A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6234147B2 (2
Inventor
Yoichi Tamaoki
Hisayuki Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14890379A priority Critical patent/JPS5671950A/ja
Publication of JPS5671950A publication Critical patent/JPS5671950A/ja
Publication of JPS6234147B2 publication Critical patent/JPS6234147B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019—Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP14890379A 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit Granted JPS5671950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14890379A JPS5671950A (en) 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14890379A JPS5671950A (en) 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP9811088A Division JPS63288044A (ja) 1988-04-22 1988-04-22 半導体装置

Publications (2)

Publication Number Publication Date
JPS5671950A true JPS5671950A (en) 1981-06-15
JPS6234147B2 JPS6234147B2 (2) 1987-07-24

Family

ID=15463240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14890379A Granted JPS5671950A (en) 1979-11-19 1979-11-19 Manufacture of integrated semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS5671950A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4804641A (en) * 1985-09-30 1989-02-14 Siemens Aktiengesellschaft Method for limiting chippage when sawing a semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4804641A (en) * 1985-09-30 1989-02-14 Siemens Aktiengesellschaft Method for limiting chippage when sawing a semiconductor wafer

Also Published As

Publication number Publication date
JPS6234147B2 (2) 1987-07-24

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