JPS5671979A - Static induction transistor and preparation method thereof - Google Patents

Static induction transistor and preparation method thereof

Info

Publication number
JPS5671979A
JPS5671979A JP14885479A JP14885479A JPS5671979A JP S5671979 A JPS5671979 A JP S5671979A JP 14885479 A JP14885479 A JP 14885479A JP 14885479 A JP14885479 A JP 14885479A JP S5671979 A JPS5671979 A JP S5671979A
Authority
JP
Japan
Prior art keywords
sio2
layer
poly
gate
selectively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14885479A
Other languages
Japanese (ja)
Inventor
Hideaki Ikoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14885479A priority Critical patent/JPS5671979A/en
Publication of JPS5671979A publication Critical patent/JPS5671979A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain an SIT having a high integration and a low consumption electric power by a method wherein a drain layer is arranged in an equal distance from a part where a P-N junction face separating a gate from a channel is in contact with a principal surface and on the surface thereof, a doped poly Si of high concentration is installed. CONSTITUTION:Taking an N<+> substrate 201 as a source, an N<-> epitaxial layer is laid thereupon and the substrate is exposed in a given area 204 and further, poly Si 205 is piled thereupon and it is oxidized to form a SiO2 film 6. Next thereto, two layer films of a Si3N4 207 and CVD-SiO2 208 are selectively formed and taking this as a mask, B ion is injectd. A heat processing is performed and a gate layer 210 and a channel 211 are formed. SiO2 212 is etched and a side of SiO2 206 is also etched, and a film 206' remains. Next thereto, the 205 is completely changed into SiO2 212 and the films 207 and 206' are removed, then, an As ion is selectively injected into a poly Si 205'. A heat processing is performed to form a drain 214. An opening 215 is selectively performed to form electrodes 216-218. With this constitution, integration degree is improved by means of a self matching method, and gate drains separate and a junction capacity is reduced, thus, lowering consumption electric power.
JP14885479A 1979-11-19 1979-11-19 Static induction transistor and preparation method thereof Pending JPS5671979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14885479A JPS5671979A (en) 1979-11-19 1979-11-19 Static induction transistor and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14885479A JPS5671979A (en) 1979-11-19 1979-11-19 Static induction transistor and preparation method thereof

Publications (1)

Publication Number Publication Date
JPS5671979A true JPS5671979A (en) 1981-06-15

Family

ID=15462218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14885479A Pending JPS5671979A (en) 1979-11-19 1979-11-19 Static induction transistor and preparation method thereof

Country Status (1)

Country Link
JP (1) JPS5671979A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4009675A1 (en) * 1989-03-28 1990-10-04 Matsushita Electric Works Ltd METHOD FOR THE PRODUCTION OF INFLUENCE SEMICONDUCTOR COMPONENTS AND SEMICONDUCTOR COMPONENT PRODUCED BY THIS
US5177029A (en) * 1989-03-28 1993-01-05 Matsushita Electric Works, Ltd. Method for manufacturing static induction type semiconductor device enhancement mode power

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4009675A1 (en) * 1989-03-28 1990-10-04 Matsushita Electric Works Ltd METHOD FOR THE PRODUCTION OF INFLUENCE SEMICONDUCTOR COMPONENTS AND SEMICONDUCTOR COMPONENT PRODUCED BY THIS
US5177029A (en) * 1989-03-28 1993-01-05 Matsushita Electric Works, Ltd. Method for manufacturing static induction type semiconductor device enhancement mode power
DE4009675C2 (en) * 1989-03-28 1995-04-06 Matsushita Electric Works Ltd Method for producing a field-controlled thyristor and thyristor produced therewith with stable withstand voltage characteristics

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