JPS5679337A - Data comparator - Google Patents

Data comparator

Info

Publication number
JPS5679337A
JPS5679337A JP15533979A JP15533979A JPS5679337A JP S5679337 A JPS5679337 A JP S5679337A JP 15533979 A JP15533979 A JP 15533979A JP 15533979 A JP15533979 A JP 15533979A JP S5679337 A JPS5679337 A JP S5679337A
Authority
JP
Japan
Prior art keywords
terminal
signal
output
logical
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15533979A
Other languages
Japanese (ja)
Inventor
Koichi Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15533979A priority Critical patent/JPS5679337A/en
Publication of JPS5679337A publication Critical patent/JPS5679337A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To exactly detect that an output signal is correct when the potential of the output signal has been varied due to oscillation, etc. in the prescribed time, by continuing to test the output signal of the apparatus to be tested while a gate opening and closing signal is being input.
CONSTITUTION: A digital signal is provided to the Dout terminal of the comparators 11a, 11b, it is provided to the logical elements 12a, 12b by which the first logial value obtained from the level comparison part 1 is compared with a Data signal which is known expected value, and moreover a gate opening and closing signal Gata for controlling the comparison time is provided through the gate terminal. The second logical value obtained by said logical elements 12a, 12b and the logical element 13 is input to the set terminal S of the RS type FF16 continuously during the holding time. A reset signal is provided to the reset terminal R of this FF16 through the PR terminal, an FD signal showing the result of the functional test is output from the output terminal 9 of the FF16, and the logical value of a digital signal which has been input to the RD terminal of the exclusive "or" element 17 is output, so that a correct logical value can be detected even if the potential is varied due to oscillation, etc. in the prescribed time.
COPYRIGHT: (C)1981,JPO&Japio
JP15533979A 1979-11-30 1979-11-30 Data comparator Pending JPS5679337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15533979A JPS5679337A (en) 1979-11-30 1979-11-30 Data comparator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15533979A JPS5679337A (en) 1979-11-30 1979-11-30 Data comparator

Publications (1)

Publication Number Publication Date
JPS5679337A true JPS5679337A (en) 1981-06-29

Family

ID=15603721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15533979A Pending JPS5679337A (en) 1979-11-30 1979-11-30 Data comparator

Country Status (1)

Country Link
JP (1) JPS5679337A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434711B1 (en) * 1996-07-19 2004-09-04 주식회사 하이닉스반도체 Serial data comparator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434711B1 (en) * 1996-07-19 2004-09-04 주식회사 하이닉스반도체 Serial data comparator

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