JPS5680867A - Memory system - Google Patents

Memory system

Info

Publication number
JPS5680867A
JPS5680867A JP15614479A JP15614479A JPS5680867A JP S5680867 A JPS5680867 A JP S5680867A JP 15614479 A JP15614479 A JP 15614479A JP 15614479 A JP15614479 A JP 15614479A JP S5680867 A JPS5680867 A JP S5680867A
Authority
JP
Japan
Prior art keywords
data
error
memory
effective bit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15614479A
Other languages
Japanese (ja)
Inventor
Akihiko Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15614479A priority Critical patent/JPS5680867A/en
Publication of JPS5680867A publication Critical patent/JPS5680867A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make possible the prohibition of using the data including error by making invalid the bit indicating the effectivity of the data through a reading data from the main memory device in which the error is detected and storing it in the buffer memory.
CONSTITUTION: When the address of the data required by CPU20 is set to the address register 1, if there is no data corresponding to the buffer memory 4 and a hit output is not generated, the data block including the data of the address designated through a control circuit 13 is read out from a main memory device 3 and stored in a memory 4. In this case, the respective word data of the data block read from the device 3 is parity-checked by an error inspection circuit 14 and when the error is detected, the effective bit of the memory 4 is changed from 1 to 0 through an effective bit reset circuit 15. Accordingly, during the processing thereafter, in accordance with the effective bit of the memory 4, the use of the data including the error is prohibited and the generation such as erroneous processing, etc., is prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP15614479A 1979-11-30 1979-11-30 Memory system Pending JPS5680867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15614479A JPS5680867A (en) 1979-11-30 1979-11-30 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15614479A JPS5680867A (en) 1979-11-30 1979-11-30 Memory system

Publications (1)

Publication Number Publication Date
JPS5680867A true JPS5680867A (en) 1981-07-02

Family

ID=15621282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15614479A Pending JPS5680867A (en) 1979-11-30 1979-11-30 Memory system

Country Status (1)

Country Link
JP (1) JPS5680867A (en)

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