JPS5690268A - Testing method for ic memory - Google Patents

Testing method for ic memory

Info

Publication number
JPS5690268A
JPS5690268A JP16798879A JP16798879A JPS5690268A JP S5690268 A JPS5690268 A JP S5690268A JP 16798879 A JP16798879 A JP 16798879A JP 16798879 A JP16798879 A JP 16798879A JP S5690268 A JPS5690268 A JP S5690268A
Authority
JP
Japan
Prior art keywords
skew
memory
signal
indented
wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16798879A
Other languages
Japanese (ja)
Inventor
Takemi Igarashi
Toshihiro Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16798879A priority Critical patent/JPS5690268A/en
Publication of JPS5690268A publication Critical patent/JPS5690268A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To enable performing a test for detecting an effect by skew by giving asynchronous skew between bit signals composing an address signal at a time when the address signal is shifted.
CONSTITUTION: A testing device 1 for IC memory and an IC memory 2 to be tested transmit and receive a signal required for signalling between them through a buffer 8. To the line receiver 7 of a skew generating circuit 4 are inputted a signal line 3 transmitting the signal and a signal line 4 transmitting the output of a threshold potential generating circuit 5 generating an indented wave. By making threshold potential be changed with time by the indented wave in this way, the timing of the start of transition can be set. Therefore, by making the generation of the indented wave reproducible constantly, the test detecting the effect by the skew by giving the skew to a memory address is made possible when the function of the IC memory 2 is tested.
COPYRIGHT: (C)1981,JPO&Japio
JP16798879A 1979-12-24 1979-12-24 Testing method for ic memory Pending JPS5690268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16798879A JPS5690268A (en) 1979-12-24 1979-12-24 Testing method for ic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16798879A JPS5690268A (en) 1979-12-24 1979-12-24 Testing method for ic memory

Publications (1)

Publication Number Publication Date
JPS5690268A true JPS5690268A (en) 1981-07-22

Family

ID=15859712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16798879A Pending JPS5690268A (en) 1979-12-24 1979-12-24 Testing method for ic memory

Country Status (1)

Country Link
JP (1) JPS5690268A (en)

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