JPS5693431A - Bootstrap output circuit - Google Patents

Bootstrap output circuit

Info

Publication number
JPS5693431A
JPS5693431A JP16933479A JP16933479A JPS5693431A JP S5693431 A JPS5693431 A JP S5693431A JP 16933479 A JP16933479 A JP 16933479A JP 16933479 A JP16933479 A JP 16933479A JP S5693431 A JPS5693431 A JP S5693431A
Authority
JP
Japan
Prior art keywords
output
circuit
misfets
driving
output circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16933479A
Other languages
Japanese (ja)
Inventor
Tsuneo Ito
Kotaro Nishimura
Hiroaki Kotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16933479A priority Critical patent/JPS5693431A/en
Publication of JPS5693431A publication Critical patent/JPS5693431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To operate the output circuit at an early timing to make the operation high-speed, by driving the output circuit by the inversion signal of a short delay time and by driving the circuit for bootstrap by the inversion signal of a long delay time. CONSTITUTION:The output circuit of the address decoder circuit is formed by depletion loas MISFETQ1 and enhancement driving MISFETs Q2-Q4 to which address input signals ao-an are input respectively. The inverting circuit which inverts the address decoder output in a high speed is formed by FETQ9 and FETQ10. Then, push-pull output MISFETs Q15 and Q14 constituted by enhancement MISFETs which form the output signal are driven by the inversion output and the decoder output.
JP16933479A 1979-12-27 1979-12-27 Bootstrap output circuit Pending JPS5693431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16933479A JPS5693431A (en) 1979-12-27 1979-12-27 Bootstrap output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16933479A JPS5693431A (en) 1979-12-27 1979-12-27 Bootstrap output circuit

Publications (1)

Publication Number Publication Date
JPS5693431A true JPS5693431A (en) 1981-07-29

Family

ID=15884618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16933479A Pending JPS5693431A (en) 1979-12-27 1979-12-27 Bootstrap output circuit

Country Status (1)

Country Link
JP (1) JPS5693431A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756982A (en) * 1993-08-13 1995-03-03 Fujitsu Ltd Layout method and layoutability evaluation device
JP2002335153A (en) * 2001-05-11 2002-11-22 Semiconductor Energy Lab Co Ltd Pulse output circuit, shift register, and display device
US7362139B2 (en) 2001-07-30 2008-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2010061800A (en) * 2009-12-01 2010-03-18 Semiconductor Energy Lab Co Ltd Pulse output circuit and display device
DE112009005393B4 (en) * 2009-11-24 2014-02-13 Epcos Ag Low current logic plus driver circuit
JP2015065658A (en) * 2014-09-29 2015-04-09 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2016027706A (en) * 2015-08-03 2016-02-18 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2017076999A (en) * 2016-11-24 2017-04-20 株式会社半導体エネルギー研究所 Semiconductor device
JP2017153080A (en) * 2017-02-23 2017-08-31 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2019133735A (en) * 2019-02-15 2019-08-08 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756982A (en) * 1993-08-13 1995-03-03 Fujitsu Ltd Layout method and layoutability evaluation device
US8786533B2 (en) 2001-05-11 2014-07-22 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
JP2002335153A (en) * 2001-05-11 2002-11-22 Semiconductor Energy Lab Co Ltd Pulse output circuit, shift register, and display device
US10916319B2 (en) 2001-05-11 2021-02-09 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US10424390B2 (en) 2001-05-11 2019-09-24 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US10109368B2 (en) 2001-05-11 2018-10-23 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US7710384B2 (en) 2001-05-11 2010-05-04 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US8264445B2 (en) 2001-05-11 2012-09-11 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US20130057161A1 (en) 2001-05-11 2013-03-07 Semiconductor Energy Laboratory Co., Ltd. Pulse Output Circuit, Shift Register and Display Device
US9812218B2 (en) 2001-05-11 2017-11-07 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US9496291B2 (en) 2001-05-11 2016-11-15 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
US9105520B2 (en) 2001-05-11 2015-08-11 Semiconductor Energy Laboratory Co., Ltd. Pulse output circuit, shift register and display device
USRE43401E1 (en) 2001-07-30 2012-05-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
USRE44657E1 (en) 2001-07-30 2013-12-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
USRE41215E1 (en) 2001-07-30 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7362139B2 (en) 2001-07-30 2008-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8686752B2 (en) 2009-11-24 2014-04-01 Epcos Ag Low-current logic plus driver circuit
DE112009005393B4 (en) * 2009-11-24 2014-02-13 Epcos Ag Low current logic plus driver circuit
JP2010061800A (en) * 2009-12-01 2010-03-18 Semiconductor Energy Lab Co Ltd Pulse output circuit and display device
JP2015065658A (en) * 2014-09-29 2015-04-09 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2016027706A (en) * 2015-08-03 2016-02-18 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2017076999A (en) * 2016-11-24 2017-04-20 株式会社半導体エネルギー研究所 Semiconductor device
JP2017153080A (en) * 2017-02-23 2017-08-31 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2019133735A (en) * 2019-02-15 2019-08-08 株式会社半導体エネルギー研究所 Semiconductor device

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