JPS57129558A - Setting circuit of stop bit number - Google Patents
Setting circuit of stop bit numberInfo
- Publication number
- JPS57129558A JPS57129558A JP56015538A JP1553881A JPS57129558A JP S57129558 A JPS57129558 A JP S57129558A JP 56015538 A JP56015538 A JP 56015538A JP 1553881 A JP1553881 A JP 1553881A JP S57129558 A JPS57129558 A JP S57129558A
- Authority
- JP
- Japan
- Prior art keywords
- divider
- output
- stop bit
- selector
- divides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000284 extract Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/24—Relay circuits using discharge tubes or semiconductor devices
- H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
- H04L25/245—Relay circuits using discharge tubes or semiconductor devices with retiming for start-stop signals
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To set a stop bit at an optional length, by switching a selector to a different frequency divider only in the case of the stop bit and supplying the output of the selector to a prescribed frequency divider. CONSTITUTION:A divider 2 divides the output of a clock generating circuit 1 down to 1/m (m>=1), and a divider 2B divides an input signal down to 1/2. Furthermore a divider 2C divides the input signal down to 1/n (n>=, mnot equal to n) and works only in the case of a stop bit SP. A selector 3 switches the output between the dividers 2A and 2C, and the output of the selector 3 is fed to the divider 2b. The selector 3 is controlled by a gate which uses a bit selection signal given from a terminal 4 and the signal given from a decoder 5 as an input. An output terminal 7 extracts the output of the divider 2B in the form of a transmitting timing signal. In such a way, a stop bit can be set at an optional length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56015538A JPS57129558A (en) | 1981-02-04 | 1981-02-04 | Setting circuit of stop bit number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56015538A JPS57129558A (en) | 1981-02-04 | 1981-02-04 | Setting circuit of stop bit number |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57129558A true JPS57129558A (en) | 1982-08-11 |
| JPH0136293B2 JPH0136293B2 (en) | 1989-07-31 |
Family
ID=11891570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56015538A Granted JPS57129558A (en) | 1981-02-04 | 1981-02-04 | Setting circuit of stop bit number |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57129558A (en) |
-
1981
- 1981-02-04 JP JP56015538A patent/JPS57129558A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0136293B2 (en) | 1989-07-31 |
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