JPS5713755A - Manufacture of semiconductor memory device - Google Patents

Manufacture of semiconductor memory device

Info

Publication number
JPS5713755A
JPS5713755A JP8937580A JP8937580A JPS5713755A JP S5713755 A JPS5713755 A JP S5713755A JP 8937580 A JP8937580 A JP 8937580A JP 8937580 A JP8937580 A JP 8937580A JP S5713755 A JPS5713755 A JP S5713755A
Authority
JP
Japan
Prior art keywords
film
bit wire
wire
silicide
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8937580A
Other languages
Japanese (ja)
Other versions
JPS5836505B2 (en
Inventor
Shinichi Inoue
Nobuo Toyokura
Hajime Ishikawa
Hiroshi Horie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55089375A priority Critical patent/JPS5836505B2/en
Publication of JPS5713755A publication Critical patent/JPS5713755A/en
Publication of JPS5836505B2 publication Critical patent/JPS5836505B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce the propagation signal delay of a semiconductor memory device having a memory cell mode of one transistor and one capacitor by forming a transfer gate electrode and a partial wire of a bit wire of impurity-containing high melting point metallic silicide. CONSTITUTION:An Mo silicide film 4 is selectively formed on a p type Si substrate 1 having a field oxidized film 2 and a gate oxidized film 3 as a capacitor electrode. The film 3 is patterned to expose a part 3A of the surface of the substrate, and the overall surface is formed with a thermally oxidized film 5. The film 5 on the region to be formed with a bit wire is removed, and a phosphorus-containing Mo silicide film of doner impurity is formed. The Mo film is patterned, and a transfer gate electrode 6G and a bit wire 6B are formed. Arsenic is injected to form an n<+> type active region 7. Thus, the resistance value of the bit wire is reduced to reduce the propagation signal delay.
JP55089375A 1980-06-30 1980-06-30 Method for manufacturing semiconductor memory device Expired JPS5836505B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55089375A JPS5836505B2 (en) 1980-06-30 1980-06-30 Method for manufacturing semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55089375A JPS5836505B2 (en) 1980-06-30 1980-06-30 Method for manufacturing semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS5713755A true JPS5713755A (en) 1982-01-23
JPS5836505B2 JPS5836505B2 (en) 1983-08-09

Family

ID=13968932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55089375A Expired JPS5836505B2 (en) 1980-06-30 1980-06-30 Method for manufacturing semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5836505B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450620A (en) * 1983-02-18 1984-05-29 Bell Telephone Laboratories, Incorporated Fabrication of MOS integrated circuit devices
JPS6014852U (en) * 1983-07-07 1985-01-31 屋敷　静雄 Driver with sliding door
JPH02147393U (en) * 1989-05-17 1990-12-14
JPH06247476A (en) * 1993-02-13 1994-09-06 Boehringer Mannheim Gmbh Liquid preparation equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450620A (en) * 1983-02-18 1984-05-29 Bell Telephone Laboratories, Incorporated Fabrication of MOS integrated circuit devices
JPS6014852U (en) * 1983-07-07 1985-01-31 屋敷　静雄 Driver with sliding door
JPH02147393U (en) * 1989-05-17 1990-12-14
JPH06247476A (en) * 1993-02-13 1994-09-06 Boehringer Mannheim Gmbh Liquid preparation equipment

Also Published As

Publication number Publication date
JPS5836505B2 (en) 1983-08-09

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