JPS566464A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS566464A
JPS566464A JP8112679A JP8112679A JPS566464A JP S566464 A JPS566464 A JP S566464A JP 8112679 A JP8112679 A JP 8112679A JP 8112679 A JP8112679 A JP 8112679A JP S566464 A JPS566464 A JP S566464A
Authority
JP
Japan
Prior art keywords
layer
diffused
oxide film
polycrystalline silicon
low density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8112679A
Other languages
Japanese (ja)
Other versions
JPS5826177B2 (en
Inventor
Shiyouji Ariizumi
Yasushi Fukatsu
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54081126A priority Critical patent/JPS5826177B2/en
Publication of JPS566464A publication Critical patent/JPS566464A/en
Publication of JPS5826177B2 publication Critical patent/JPS5826177B2/en
Priority to US06/545,002 priority patent/US4475964A/en
Priority to US06/665,081 priority patent/US4558343A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the density of a semiconductor device by making at least one end of a low density layer of high specific resistance direct contact with a polycrystalline silicon layer diffused with impurity in high density connected to a diffused layer formed already with a driving transistor. CONSTITUTION:Source and drain diffused regions 22 and 23 extended from a main surface of a semiconductor substrate 21 formed with a field oxide film 20 are formed in the substrate 21, and a gate electrode 25a is formed through a gate oxide layer 24 on the exposed surfaces between the regions 22 and 23. Further, a polycrystalline silicon layer 25b diffused with impurity in high density directly contacted with the drain diffused region 23 at one end is formed on the surface of the field oxide film 20, a low density layer 26 directly contacted with the polycrystalline silicon layer 25b is formed through a silicon oxide layer 27, a silicon oxide film 29 is coated excluding the pickup portion of a wiring metal on the surfaces of the gate electrode and the low density layer 26, and a protective layer 30 is further formed thereon.
JP54081126A 1979-02-20 1979-06-27 Manufacturing method of semiconductor device Expired JPS5826177B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP54081126A JPS5826177B2 (en) 1979-06-27 1979-06-27 Manufacturing method of semiconductor device
US06/545,002 US4475964A (en) 1979-02-20 1983-10-24 Method of manufacturing a semiconductor device
US06/665,081 US4558343A (en) 1979-02-20 1984-10-26 Semiconductor device having a high resistivity layer in direct contact with a polycrystalline silicon layer of high impurity concentration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54081126A JPS5826177B2 (en) 1979-06-27 1979-06-27 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS566464A true JPS566464A (en) 1981-01-23
JPS5826177B2 JPS5826177B2 (en) 1983-06-01

Family

ID=13737691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54081126A Expired JPS5826177B2 (en) 1979-02-20 1979-06-27 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5826177B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244832A (en) * 1985-10-16 1993-09-14 Texas Instruments Incorporated Method for fabricating a poly emitter logic array and apparatus produced thereby

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195084U (en) * 1987-12-16 1989-06-22

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024230A (en) * 1973-02-16 1975-03-15
JPS50134389A (en) * 1974-04-10 1975-10-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024230A (en) * 1973-02-16 1975-03-15
JPS50134389A (en) * 1974-04-10 1975-10-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244832A (en) * 1985-10-16 1993-09-14 Texas Instruments Incorporated Method for fabricating a poly emitter logic array and apparatus produced thereby

Also Published As

Publication number Publication date
JPS5826177B2 (en) 1983-06-01

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