JPS5714944A - Input/output sysytem - Google Patents
Input/output sysytemInfo
- Publication number
- JPS5714944A JPS5714944A JP9013680A JP9013680A JPS5714944A JP S5714944 A JPS5714944 A JP S5714944A JP 9013680 A JP9013680 A JP 9013680A JP 9013680 A JP9013680 A JP 9013680A JP S5714944 A JPS5714944 A JP S5714944A
- Authority
- JP
- Japan
- Prior art keywords
- data
- output
- circuit
- code
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer And Data Communications (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PURPOSE:To enable a central processor to process an input/output data in the form of a fixed length data in a system using a variable length code, by putting an invalid code into an idle region. CONSTITUTION:A data process system comprises with a mutual connection among an input device 1, a central processor 2 and an output device 3 via data buses 4 and 5. The variable length character code is transferred by a byte in the device 1 to a buffer register 7 from a data buffer 6 via a counter circuit 9. In this case, the circuit 9 counts the number of bytes of the character code to be transferred to the register 7 and then report the end of transfer to a data control circuit 10. Receiving this report, the circuit 10 puts an invalid code into the rest part of the register 7 and then transmits it to the processor 2 in the form of a fixed length daga. The device 2 eliminates the invalid code for delivery of an output through an output deciding circuit 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55090136A JPS607292B2 (en) | 1980-07-02 | 1980-07-02 | Input/output method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55090136A JPS607292B2 (en) | 1980-07-02 | 1980-07-02 | Input/output method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5714944A true JPS5714944A (en) | 1982-01-26 |
| JPS607292B2 JPS607292B2 (en) | 1985-02-23 |
Family
ID=13990085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55090136A Expired JPS607292B2 (en) | 1980-07-02 | 1980-07-02 | Input/output method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607292B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04343646A (en) * | 1991-05-20 | 1992-11-30 | Kilony Sangyo Kk | Contact for copying detector |
-
1980
- 1980-07-02 JP JP55090136A patent/JPS607292B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04343646A (en) * | 1991-05-20 | 1992-11-30 | Kilony Sangyo Kk | Contact for copying detector |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS607292B2 (en) | 1985-02-23 |
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