JPS57194560A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS57194560A
JPS57194560A JP56080262A JP8026281A JPS57194560A JP S57194560 A JPS57194560 A JP S57194560A JP 56080262 A JP56080262 A JP 56080262A JP 8026281 A JP8026281 A JP 8026281A JP S57194560 A JPS57194560 A JP S57194560A
Authority
JP
Japan
Prior art keywords
leads
internal
shortcircuiting
edge
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56080262A
Other languages
Japanese (ja)
Inventor
Toshio Ikegami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP56080262A priority Critical patent/JPS57194560A/en
Publication of JPS57194560A publication Critical patent/JPS57194560A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/458—Materials of insulating layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the leads from shortcircuiting improving the quality level by a method wherein, when the semiconductor element and the internal leading element are connected by means of the bonding wire, the U type insulating projections are provided on the edge of the internal leading elements. CONSTITUTION:The semiconductor element 4 provided on the element base 3 and the multiple internal leads 1 are connected by means of the bonding wire 2 and the U type insulating projections 5 are provided on the edge of the internal leads 1. Through these procedures, no shortcircuiting happens even if the current generated after sealing by resin comes into contact with the adjoining leads 2.
JP56080262A 1981-05-27 1981-05-27 Lead frame Pending JPS57194560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56080262A JPS57194560A (en) 1981-05-27 1981-05-27 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56080262A JPS57194560A (en) 1981-05-27 1981-05-27 Lead frame

Publications (1)

Publication Number Publication Date
JPS57194560A true JPS57194560A (en) 1982-11-30

Family

ID=13713394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56080262A Pending JPS57194560A (en) 1981-05-27 1981-05-27 Lead frame

Country Status (1)

Country Link
JP (1) JPS57194560A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072280A (en) * 1989-10-23 1991-12-10 Nec Corporation Resin sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072280A (en) * 1989-10-23 1991-12-10 Nec Corporation Resin sealed semiconductor device

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