JPS5748241A - Bonding method for chip - Google Patents

Bonding method for chip

Info

Publication number
JPS5748241A
JPS5748241A JP55124182A JP12418280A JPS5748241A JP S5748241 A JPS5748241 A JP S5748241A JP 55124182 A JP55124182 A JP 55124182A JP 12418280 A JP12418280 A JP 12418280A JP S5748241 A JPS5748241 A JP S5748241A
Authority
JP
Japan
Prior art keywords
chip
collet
band
package
band surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55124182A
Other languages
Japanese (ja)
Other versions
JPS636141B2 (en
Inventor
Tsuyoshi Aoki
Junichi Yano
Takehisa Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55124182A priority Critical patent/JPS5748241A/en
Publication of JPS5748241A publication Critical patent/JPS5748241A/en
Publication of JPS636141B2 publication Critical patent/JPS636141B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0446—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To perform uniform brazing and improve reliability, by a method wherein in chip bonding, the collet axis angle is corrected according to the inclination of the chip band surface of a package so that said chip band surface and the chip lower surface are held in parallel to each other. CONSTITUTION:Being clamped between leg parts 1 and 1' of a collet comprising a tweezer mechanism, a chip 2 is carried to above a chip band 5 of a package 4 and lowered so as to be mounted thereon. In this case, by means of a foreign substance 8 placed between a holder 7 and the package 4, the collet axis Y-Y' is inclined to the vertical plane at a given angle theta. With the collet leg parts opened, the collet is further lowered, and when the chip 2 abuts on the band, the collet axis is corrected so as to be perpendicular to the band surface. With the correction angle theta maintained, the chip is clamped again and slid contacting with the band surface so as to be scrubbed. Thereby, it is possible to perform uniform brazing without damaging the edge portions.
JP55124182A 1980-09-08 1980-09-08 Bonding method for chip Granted JPS5748241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55124182A JPS5748241A (en) 1980-09-08 1980-09-08 Bonding method for chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55124182A JPS5748241A (en) 1980-09-08 1980-09-08 Bonding method for chip

Publications (2)

Publication Number Publication Date
JPS5748241A true JPS5748241A (en) 1982-03-19
JPS636141B2 JPS636141B2 (en) 1988-02-08

Family

ID=14879001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55124182A Granted JPS5748241A (en) 1980-09-08 1980-09-08 Bonding method for chip

Country Status (1)

Country Link
JP (1) JPS5748241A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294573A (en) * 1999-04-07 2000-10-20 Casio Comput Co Ltd Bonding equipment
US6750431B2 (en) * 2002-07-24 2004-06-15 Hakko Corporation Electric component removing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294573A (en) * 1999-04-07 2000-10-20 Casio Comput Co Ltd Bonding equipment
US6750431B2 (en) * 2002-07-24 2004-06-15 Hakko Corporation Electric component removing device

Also Published As

Publication number Publication date
JPS636141B2 (en) 1988-02-08

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