JPS5752150A - Semiconductor device with element forming region surrounded by porous silicon oxide - Google Patents

Semiconductor device with element forming region surrounded by porous silicon oxide

Info

Publication number
JPS5752150A
JPS5752150A JP55127109A JP12710980A JPS5752150A JP S5752150 A JPS5752150 A JP S5752150A JP 55127109 A JP55127109 A JP 55127109A JP 12710980 A JP12710980 A JP 12710980A JP S5752150 A JPS5752150 A JP S5752150A
Authority
JP
Japan
Prior art keywords
region
porous silicon
silicon oxide
element forming
forming region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55127109A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6221270B2 (2
Inventor
Kazuo Imai
Susumu Muramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55127109A priority Critical patent/JPS5752150A/ja
Publication of JPS5752150A publication Critical patent/JPS5752150A/ja
Publication of JPS6221270B2 publication Critical patent/JPS6221270B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/191—Preparing SOI wafers using full isolation by porous oxide silicon [FIPOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
JP55127109A 1980-09-16 1980-09-16 Semiconductor device with element forming region surrounded by porous silicon oxide Granted JPS5752150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55127109A JPS5752150A (en) 1980-09-16 1980-09-16 Semiconductor device with element forming region surrounded by porous silicon oxide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55127109A JPS5752150A (en) 1980-09-16 1980-09-16 Semiconductor device with element forming region surrounded by porous silicon oxide

Publications (2)

Publication Number Publication Date
JPS5752150A true JPS5752150A (en) 1982-03-27
JPS6221270B2 JPS6221270B2 (2) 1987-05-12

Family

ID=14951820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55127109A Granted JPS5752150A (en) 1980-09-16 1980-09-16 Semiconductor device with element forming region surrounded by porous silicon oxide

Country Status (1)

Country Link
JP (1) JPS5752150A (2)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158869A (ja) * 1986-12-23 1988-07-01 Oki Electric Ind Co Ltd 半導体メモリ装置
WO2004036650A1 (en) * 2002-08-05 2004-04-29 Telephus Inc. High frequency semiconductor device and producing the same
WO2004100256A1 (de) * 2003-05-07 2004-11-18 Robert Bosch Gmbh Vorrichtung mit einer halbleiterschaltung

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158869A (ja) * 1986-12-23 1988-07-01 Oki Electric Ind Co Ltd 半導体メモリ装置
WO2004036650A1 (en) * 2002-08-05 2004-04-29 Telephus Inc. High frequency semiconductor device and producing the same
WO2004100256A1 (de) * 2003-05-07 2004-11-18 Robert Bosch Gmbh Vorrichtung mit einer halbleiterschaltung

Also Published As

Publication number Publication date
JPS6221270B2 (2) 1987-05-12

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