JPS5754354A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5754354A
JPS5754354A JP55130416A JP13041680A JPS5754354A JP S5754354 A JPS5754354 A JP S5754354A JP 55130416 A JP55130416 A JP 55130416A JP 13041680 A JP13041680 A JP 13041680A JP S5754354 A JPS5754354 A JP S5754354A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
terminals
power source
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55130416A
Other languages
Japanese (ja)
Inventor
Masahiro Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP55130416A priority Critical patent/JPS5754354A/en
Publication of JPS5754354A publication Critical patent/JPS5754354A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve efficiency of equipment of a semiconductor integrated circuit device by a method wherein outside lead out terminals of the semiconductor integrated circuit device are so arranged as positive electric power source terminals, negative electric power source terminals, and input and output terminals are positioned in symmetry to a terminal at the center position or in rotation symmetry to a package. CONSTITUTION:At a single line type 9 pins package integrated circuit device building in signal processing circuits 5, 6, for example, a center terminal (5) is selected as a positive electrode power source, a terminal (1) and a terminal (9) are made as negative electric power source terminals, and the other signal terminals are arranged symmetrically to the terminal (5). At a dual line type integrated circuit device building in operational amplifier circuits 7-10, electric power source terminals Vcc and Vee, and signal terminals are arranged rotation symmetrically to the package as shown in the figure. Accordingly when the semiconductor integrated circuit device is to be equipped to a printed substrate, socket, etc., to pay attention to directional property becomes as needless, and efficiency of equipment can be enhanced.
JP55130416A 1980-09-18 1980-09-18 Semiconductor integrated circuit device Pending JPS5754354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55130416A JPS5754354A (en) 1980-09-18 1980-09-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55130416A JPS5754354A (en) 1980-09-18 1980-09-18 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5754354A true JPS5754354A (en) 1982-03-31

Family

ID=15033730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55130416A Pending JPS5754354A (en) 1980-09-18 1980-09-18 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5754354A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137581U (en) * 1988-03-11 1989-09-20
JP2007059884A (en) * 2005-07-22 2007-03-08 Marvell World Trade Ltd Packaging for high-speed integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137581U (en) * 1988-03-11 1989-09-20
JP2007059884A (en) * 2005-07-22 2007-03-08 Marvell World Trade Ltd Packaging for high-speed integrated circuits

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