JPS5758331A - Manufacture of semiconductor device utilizing self-aligning double diffusion - Google Patents

Manufacture of semiconductor device utilizing self-aligning double diffusion

Info

Publication number
JPS5758331A
JPS5758331A JP55133245A JP13324580A JPS5758331A JP S5758331 A JPS5758331 A JP S5758331A JP 55133245 A JP55133245 A JP 55133245A JP 13324580 A JP13324580 A JP 13324580A JP S5758331 A JPS5758331 A JP S5758331A
Authority
JP
Japan
Prior art keywords
regions
region
manufacture
semiconductor device
shortcircuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55133245A
Other languages
Japanese (ja)
Other versions
JPH0337298B2 (en
Inventor
Akira Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP55133245A priority Critical patent/JPS5758331A/en
Publication of JPS5758331A publication Critical patent/JPS5758331A/en
Publication of JPH0337298B2 publication Critical patent/JPH0337298B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device of shortcircuit electrode structure by interposing double electrodes between regions to form two same conductive type regions, thereby reducing the step of selectively diffusing or masking it. CONSTITUTION:An insulating film 12 is formed on the surface of an N type semiconductor region 11 and openings 13, 14 are formed at both sides of an isolation insulating film 12a. Then, P type regions 15, 16 are formed to form double region 20 through the openings 13, 14. Subsequently, N type regions 17, 18 are formed in the regions 15, 16 through the openings 13, 14. In this step, the region 20 is slightly expanded. Thereafter, the film 12a is removed, and a shortcircuit electrode 19 is formed to reach from the surface of the region 17 through the surface of the region 20 to the surface of the region 18. Thus, the regions 17, 18 are maintained in isolated state, and since the region 20 is interposed between the regions 17 and 18, the shortcircuit of the regions 15, 16 and the regions 17, 18 via the electrode 19 can be readily performed. Accordingly, the steps canbe simplified and the yield can be improved.
JP55133245A 1980-09-24 1980-09-24 Manufacture of semiconductor device utilizing self-aligning double diffusion Granted JPS5758331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55133245A JPS5758331A (en) 1980-09-24 1980-09-24 Manufacture of semiconductor device utilizing self-aligning double diffusion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133245A JPS5758331A (en) 1980-09-24 1980-09-24 Manufacture of semiconductor device utilizing self-aligning double diffusion

Publications (2)

Publication Number Publication Date
JPS5758331A true JPS5758331A (en) 1982-04-08
JPH0337298B2 JPH0337298B2 (en) 1991-06-05

Family

ID=15100094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133245A Granted JPS5758331A (en) 1980-09-24 1980-09-24 Manufacture of semiconductor device utilizing self-aligning double diffusion

Country Status (1)

Country Link
JP (1) JPS5758331A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975288A (en) * 1972-11-22 1974-07-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975288A (en) * 1972-11-22 1974-07-19

Also Published As

Publication number Publication date
JPH0337298B2 (en) 1991-06-05

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