JPS5773977A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5773977A JPS5773977A JP56136445A JP13644581A JPS5773977A JP S5773977 A JPS5773977 A JP S5773977A JP 56136445 A JP56136445 A JP 56136445A JP 13644581 A JP13644581 A JP 13644581A JP S5773977 A JPS5773977 A JP S5773977A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wire
- gate
- sio2
- si3n4
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a multilayer wire without disconnection by employing an SiO2 film, an Si3N4 film, a polycrystalline Si film, etc. when forming an IGFET and freely limiting the thickness of an insulating film on the upper surface. CONSTITUTION:An SiO2 film 2 is covered on an N type Si substrate 1, a substrate surface 3 is exposed corresponding to source, drain and gate forming regions, and a gate SiO2 film 4 integral with the film 2 is covered thereon. Subsequentlu, an Si3N4 film 5, a polycrystalline Si film 6, an Si3N4 film 7 are laminated, are photoetched, and the film 7 and a film 8 made only of the film 7 are retained on the gate forming region and the wire forming region. Thereafter, with them as masks it is etched to retain the film 6, a gate 11 and a wire 10 only under the films 7, 8, are heat treated, and an SiO2 film 12 is formed at the side face. Thereafter, it is etched to remove the exposed films 5, 8, 9, P type impurity is diffused to form P type source and drain regions 14, 16, and the electrode 11 and the wire 10 are imparted with conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56136445A JPS5773977A (en) | 1981-08-31 | 1981-08-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56136445A JPS5773977A (en) | 1981-08-31 | 1981-08-31 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6887072A Division JPS5550395B2 (en) | 1972-07-08 | 1972-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5773977A true JPS5773977A (en) | 1982-05-08 |
Family
ID=15175276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56136445A Pending JPS5773977A (en) | 1981-08-31 | 1981-08-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5773977A (en) |
-
1981
- 1981-08-31 JP JP56136445A patent/JPS5773977A/en active Pending
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