JPS57747A - Digital display circuit by microcomputer - Google Patents

Digital display circuit by microcomputer

Info

Publication number
JPS57747A
JPS57747A JP7360880A JP7360880A JPS57747A JP S57747 A JPS57747 A JP S57747A JP 7360880 A JP7360880 A JP 7360880A JP 7360880 A JP7360880 A JP 7360880A JP S57747 A JPS57747 A JP S57747A
Authority
JP
Japan
Prior art keywords
addresses
terminal
ram5
level
digits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7360880A
Other languages
Japanese (ja)
Other versions
JPS6252891B2 (en
Inventor
Masaaki Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP7360880A priority Critical patent/JPS57747A/en
Publication of JPS57747A publication Critical patent/JPS57747A/en
Publication of JPS6252891B2 publication Critical patent/JPS6252891B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: To obtain a digital display circuit of simple constitution without any burden on programming, by forcibly changing addresses of an RAM in dynamic memory refresh RF mode, by using a CPU with an incorporated RF function.
CONSTITUTION: The RF terminal RESH, memory request terminal MREQ and a memory readout terminal of a CPU1 with an RF function for a dynamic RAM are at level Ls in RF mode, and their signals hold the R/W terminal of the RAM5 at a level H to place the RAM5 in readout mode. Then, inputs to addresses A4WA7 of the RAM5 go to level Hs and only the addresses A0WA2 are set to binary numerals 0W7 with an RF signal; and this data is sent to a data bus 3 to be held in a latching IC6 temporarily. Further, the addresses A0WA2 are connected to the IC6 to be used to select display digits. The latched data and the number of digits of it are decoded by a decoder IC7 and a binary decoder IC9 and a decimal number is displayed on prescribed digits of an LED display device 8.
COPYRIGHT: (C)1982,JPO&Japio
JP7360880A 1980-05-30 1980-05-30 Digital display circuit by microcomputer Granted JPS57747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7360880A JPS57747A (en) 1980-05-30 1980-05-30 Digital display circuit by microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7360880A JPS57747A (en) 1980-05-30 1980-05-30 Digital display circuit by microcomputer

Publications (2)

Publication Number Publication Date
JPS57747A true JPS57747A (en) 1982-01-05
JPS6252891B2 JPS6252891B2 (en) 1987-11-07

Family

ID=13523210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7360880A Granted JPS57747A (en) 1980-05-30 1980-05-30 Digital display circuit by microcomputer

Country Status (1)

Country Link
JP (1) JPS57747A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271689U (en) * 1985-10-25 1987-05-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271689U (en) * 1985-10-25 1987-05-07

Also Published As

Publication number Publication date
JPS6252891B2 (en) 1987-11-07

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