JPS5776848A - Mounting method for integrated circuit chip - Google Patents

Mounting method for integrated circuit chip

Info

Publication number
JPS5776848A
JPS5776848A JP55152528A JP15252880A JPS5776848A JP S5776848 A JPS5776848 A JP S5776848A JP 55152528 A JP55152528 A JP 55152528A JP 15252880 A JP15252880 A JP 15252880A JP S5776848 A JPS5776848 A JP S5776848A
Authority
JP
Japan
Prior art keywords
chip
hole
substrate
bored
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55152528A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0235464B2 (2
Inventor
Akishi Shiraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55152528A priority Critical patent/JPS5776848A/ja
Publication of JPS5776848A publication Critical patent/JPS5776848A/ja
Publication of JPH0235464B2 publication Critical patent/JPH0235464B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07327—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)
JP55152528A 1980-10-30 1980-10-30 Mounting method for integrated circuit chip Granted JPS5776848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55152528A JPS5776848A (en) 1980-10-30 1980-10-30 Mounting method for integrated circuit chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55152528A JPS5776848A (en) 1980-10-30 1980-10-30 Mounting method for integrated circuit chip

Publications (2)

Publication Number Publication Date
JPS5776848A true JPS5776848A (en) 1982-05-14
JPH0235464B2 JPH0235464B2 (2) 1990-08-10

Family

ID=15542400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55152528A Granted JPS5776848A (en) 1980-10-30 1980-10-30 Mounting method for integrated circuit chip

Country Status (1)

Country Link
JP (1) JPS5776848A (2)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089948A (ja) * 1983-10-24 1985-05-20 Toshiba Corp リ−ドフレ−ム
JPS60181072U (ja) * 1984-05-12 1985-12-02 イビデン株式会社 チツプ搭載用プリント配線基板
JPS62134938A (ja) * 1985-12-04 1987-06-18 フアオ・デ−・オ−・ア−ドルフ・シントリング・アクチエンゲゼルシヤフト 支持プレ−ト

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144871A (2) * 1974-10-15 1976-04-16 Nippon Electric Co
JPS51163867U (2) * 1975-06-19 1976-12-27

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144871A (2) * 1974-10-15 1976-04-16 Nippon Electric Co
JPS51163867U (2) * 1975-06-19 1976-12-27

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089948A (ja) * 1983-10-24 1985-05-20 Toshiba Corp リ−ドフレ−ム
JPS60181072U (ja) * 1984-05-12 1985-12-02 イビデン株式会社 チツプ搭載用プリント配線基板
JPS62134938A (ja) * 1985-12-04 1987-06-18 フアオ・デ−・オ−・ア−ドルフ・シントリング・アクチエンゲゼルシヤフト 支持プレ−ト

Also Published As

Publication number Publication date
JPH0235464B2 (2) 1990-08-10

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