JPS5776877A - Semiconductor memory device and manufacture thereof - Google Patents

Semiconductor memory device and manufacture thereof

Info

Publication number
JPS5776877A
JPS5776877A JP55152509A JP15250980A JPS5776877A JP S5776877 A JPS5776877 A JP S5776877A JP 55152509 A JP55152509 A JP 55152509A JP 15250980 A JP15250980 A JP 15250980A JP S5776877 A JPS5776877 A JP S5776877A
Authority
JP
Japan
Prior art keywords
drain region
oxide film
tunnel oxide
eeprom
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55152509A
Other languages
Japanese (ja)
Inventor
Izumi Tanaka
Takashi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55152509A priority Critical patent/JPS5776877A/en
Publication of JPS5776877A publication Critical patent/JPS5776877A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve the reliability of EEPROM (PROM in which electrical eliminating is possible) is which electrical eliminating and writing is possible by a method wherein a drain region under a tunnel oxide film is kept away by forming the drain region roughly into an L-shape and a stable tunnel oxide film is formed. CONSTITUTION:In EEPROM which is composed of a floating gate electrode 14 formed on a surface of a p type semiconductor substrate 11 with a gate insulating film 13 underneath, a control gate electrode 15, a source region 16 and a drain region 17, the roughly L-shaped drain region 17 to which a drain electrode is connected is kept away from the drain region 17' under a tunnel oxide film 20 which is formed by using properly two kinds of impurities As and P. Here two memory elements are formed symmetically and the drain regions 17, 17' form a T-shape. With above method the stable tunnel oxide film 20 is obtained and the reliability of EEPROM is improved.
JP55152509A 1980-10-30 1980-10-30 Semiconductor memory device and manufacture thereof Pending JPS5776877A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55152509A JPS5776877A (en) 1980-10-30 1980-10-30 Semiconductor memory device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55152509A JPS5776877A (en) 1980-10-30 1980-10-30 Semiconductor memory device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5776877A true JPS5776877A (en) 1982-05-14

Family

ID=15542001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55152509A Pending JPS5776877A (en) 1980-10-30 1980-10-30 Semiconductor memory device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5776877A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166079A (en) * 1984-09-25 1986-07-26 エツセジ−エツセ−アテイイ−エツセ・コンポネンテイ・エレツトロニ−チ・ソチエタ・ペル・アノニマ Durable memory cell and manufacture thereof
JPS61186945A (en) * 1985-02-15 1986-08-20 Fuji Photo Film Co Ltd Photographing device
US4861730A (en) * 1988-01-25 1989-08-29 Catalyst Semiconductor, Inc. Process for making a high density split gate nonvolatile memory cell
US5132239A (en) * 1989-09-04 1992-07-21 Sgs-Thomson Microelectronics S.R.L. Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation
US5215934A (en) * 1989-12-21 1993-06-01 Tzeng Jyh Cherng J Process for reducing program disturbance in eeprom arrays
US5284786A (en) * 1992-08-14 1994-02-08 National Semiconductor Corporation Method of making a split floating gate EEPROM cell

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166079A (en) * 1984-09-25 1986-07-26 エツセジ−エツセ−アテイイ−エツセ・コンポネンテイ・エレツトロニ−チ・ソチエタ・ペル・アノニマ Durable memory cell and manufacture thereof
JPS61186945A (en) * 1985-02-15 1986-08-20 Fuji Photo Film Co Ltd Photographing device
US4861730A (en) * 1988-01-25 1989-08-29 Catalyst Semiconductor, Inc. Process for making a high density split gate nonvolatile memory cell
US5132239A (en) * 1989-09-04 1992-07-21 Sgs-Thomson Microelectronics S.R.L. Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation
US5215934A (en) * 1989-12-21 1993-06-01 Tzeng Jyh Cherng J Process for reducing program disturbance in eeprom arrays
US5284786A (en) * 1992-08-14 1994-02-08 National Semiconductor Corporation Method of making a split floating gate EEPROM cell

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