JPS5779541A - Interprocessor communication system - Google Patents

Interprocessor communication system

Info

Publication number
JPS5779541A
JPS5779541A JP55155450A JP15545080A JPS5779541A JP S5779541 A JPS5779541 A JP S5779541A JP 55155450 A JP55155450 A JP 55155450A JP 15545080 A JP15545080 A JP 15545080A JP S5779541 A JPS5779541 A JP S5779541A
Authority
JP
Japan
Prior art keywords
processing
processors
data
transferred
communication system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55155450A
Other languages
English (en)
Inventor
Ryohei Nakano
Masakazu Baba
Toyoki Ofuji
Yoshiyuki Tokuno
Nobuyuki Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
NTT Inc
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP55155450A priority Critical patent/JPS5779541A/ja
Publication of JPS5779541A publication Critical patent/JPS5779541A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
JP55155450A 1980-11-05 1980-11-05 Interprocessor communication system Pending JPS5779541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55155450A JPS5779541A (en) 1980-11-05 1980-11-05 Interprocessor communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55155450A JPS5779541A (en) 1980-11-05 1980-11-05 Interprocessor communication system

Publications (1)

Publication Number Publication Date
JPS5779541A true JPS5779541A (en) 1982-05-18

Family

ID=15606302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55155450A Pending JPS5779541A (en) 1980-11-05 1980-11-05 Interprocessor communication system

Country Status (1)

Country Link
JP (1) JPS5779541A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168126A (ja) * 1982-03-29 1983-10-04 Fujitsu Ltd デ−タ転送制御方式
US5935204A (en) * 1989-11-08 1999-08-10 Fujitsu Limited System for a multi-processor system wherein each processor transfers a data block from cache if a cache hit and from main memory only if cache miss

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168126A (ja) * 1982-03-29 1983-10-04 Fujitsu Ltd デ−タ転送制御方式
US5935204A (en) * 1989-11-08 1999-08-10 Fujitsu Limited System for a multi-processor system wherein each processor transfers a data block from cache if a cache hit and from main memory only if cache miss

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