JPS5789230A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5789230A
JPS5789230A JP55164559A JP16455980A JPS5789230A JP S5789230 A JPS5789230 A JP S5789230A JP 55164559 A JP55164559 A JP 55164559A JP 16455980 A JP16455980 A JP 16455980A JP S5789230 A JPS5789230 A JP S5789230A
Authority
JP
Japan
Prior art keywords
tub
resin
wire
pellet
lessen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55164559A
Other languages
Japanese (ja)
Other versions
JPS6248375B2 (en
Inventor
Kazuo Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55164559A priority Critical patent/JPS5789230A/en
Publication of JPS5789230A publication Critical patent/JPS5789230A/en
Publication of JPS6248375B2 publication Critical patent/JPS6248375B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To lessen flowing resistance of resin to a wire to occur with the injection of molding resin, prevent the wire from flowing, being deformed, contacting, or being disconnected, and lessen a wire diameter. CONSTITUTION:A tub 12, which is a pellet-mounting part of a lead frame, is a square. A pellet 10 is mounted on the tub. The tub 12 is so arranged that all of its four sides make angles of 45 deg. with respect to the injecting direction of resin A. Each of four sides of the tub corresponds to the point of an inner lead 14 of a lead frame in equal intervals. Therefore, a wire 18 to connect a bonding pad 16 and an inner lead 14 of the pellet 10 is wired wholly in the forward direction to the injecting direction of resin A. The tub 12 may ge a rectangle instead of a square, or arranged at an angle except 45 deg. to the injecting direction of the resin.
JP55164559A 1980-11-25 1980-11-25 Semiconductor device Granted JPS5789230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55164559A JPS5789230A (en) 1980-11-25 1980-11-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164559A JPS5789230A (en) 1980-11-25 1980-11-25 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP63194403A Division JPH01315149A (en) 1988-08-05 1988-08-05 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5789230A true JPS5789230A (en) 1982-06-03
JPS6248375B2 JPS6248375B2 (en) 1987-10-13

Family

ID=15795458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164559A Granted JPS5789230A (en) 1980-11-25 1980-11-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5789230A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072279A (en) * 1990-10-29 1991-12-10 Delco Electronics Corporation Electrical interconnection having angular lead design
US5162265A (en) * 1990-10-29 1992-11-10 Delco Electronics Corporation Method of making an electrical interconnection having angular lead design
WO1994027320A1 (en) * 1993-05-07 1994-11-24 National Semiconductor Corporation Plastic encapsulated integrated circuit package and method of manufacturing the same
WO2001043205A1 (en) * 1999-12-09 2001-06-14 Rohm Co., Ltd. Light-emitting chip device with case and method of manufacture thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072279A (en) * 1990-10-29 1991-12-10 Delco Electronics Corporation Electrical interconnection having angular lead design
US5162265A (en) * 1990-10-29 1992-11-10 Delco Electronics Corporation Method of making an electrical interconnection having angular lead design
WO1994027320A1 (en) * 1993-05-07 1994-11-24 National Semiconductor Corporation Plastic encapsulated integrated circuit package and method of manufacturing the same
US5437095A (en) * 1993-05-07 1995-08-01 National Semiconductor Corporation Method of making plastic encapsulated integrated circuit package
WO2001043205A1 (en) * 1999-12-09 2001-06-14 Rohm Co., Ltd. Light-emitting chip device with case and method of manufacture thereof

Also Published As

Publication number Publication date
JPS6248375B2 (en) 1987-10-13

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