JPS5797634A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS5797634A
JPS5797634A JP55174923A JP17492380A JPS5797634A JP S5797634 A JPS5797634 A JP S5797634A JP 55174923 A JP55174923 A JP 55174923A JP 17492380 A JP17492380 A JP 17492380A JP S5797634 A JPS5797634 A JP S5797634A
Authority
JP
Japan
Prior art keywords
conductor pattern
substrate
insulating filler
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55174923A
Other languages
Japanese (ja)
Inventor
Katsumi Komiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP55174923A priority Critical patent/JPS5797634A/en
Publication of JPS5797634A publication Critical patent/JPS5797634A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07327—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To contrive to mount in high density and to reduce cost of a hybrid integrated circuit by a method wherein a circuit element, a part thereof has conductivity, is to be equipped to a substrate, the element is equipped to the substrate interposing an adhesive layer containing an insulating filler and being thicker than a conductor pattern between them. CONSTITUTION:Because the semiconductor element 5 is equipped to the substrate 1 interposing the adhesive layer 11 containing the insulating filler 10 having the larger outside diameter than thickness of the conductor pattern 12 between them, a finite interval exists always between the upper face of the conductor pattern 12 and the lower face of the semiconductor element 5 owing to the insulating filler being distributed in the part other than the conductor pattern to prevent electric short-circuiting. Accordingly, because to make the conductor pattern take a roundabout route is unnecessitated, density of the circuit is enhanced.
JP55174923A 1980-12-11 1980-12-11 Hybrid integrated circuit Pending JPS5797634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55174923A JPS5797634A (en) 1980-12-11 1980-12-11 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55174923A JPS5797634A (en) 1980-12-11 1980-12-11 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5797634A true JPS5797634A (en) 1982-06-17

Family

ID=15987071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55174923A Pending JPS5797634A (en) 1980-12-11 1980-12-11 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5797634A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827935U (en) * 1981-08-18 1983-02-23 株式会社村田製作所 Hybrid integrated circuit device
JPS5842940U (en) * 1981-09-16 1983-03-23 株式会社村田製作所 Hybrid integrated circuit device
JPS59136968A (en) * 1983-01-25 1984-08-06 Mitsubishi Electric Corp Hybrid integrated circuit device
JPS6181140U (en) * 1984-11-01 1986-05-29
JPS6196541U (en) * 1984-11-30 1986-06-21
US4888634A (en) * 1987-07-24 1989-12-19 Linear Technology Corporation High thermal resistance bonding material and semiconductor structures using same
JPH02201948A (en) * 1989-01-30 1990-08-10 Toshiba Corp Package of semiconductor device
JPH0626472U (en) * 1992-09-16 1994-04-12 靖仁 田中 Gimmick reel
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
WO2003067945A1 (en) * 2002-02-06 2003-08-14 Endress + Hauser Gmbh + Co. Kg Printed circuit board comprising a component

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827935U (en) * 1981-08-18 1983-02-23 株式会社村田製作所 Hybrid integrated circuit device
JPS5842940U (en) * 1981-09-16 1983-03-23 株式会社村田製作所 Hybrid integrated circuit device
JPS59136968A (en) * 1983-01-25 1984-08-06 Mitsubishi Electric Corp Hybrid integrated circuit device
JPS6181140U (en) * 1984-11-01 1986-05-29
JPS6196541U (en) * 1984-11-30 1986-06-21
US4888634A (en) * 1987-07-24 1989-12-19 Linear Technology Corporation High thermal resistance bonding material and semiconductor structures using same
JPH02201948A (en) * 1989-01-30 1990-08-10 Toshiba Corp Package of semiconductor device
JPH0626472U (en) * 1992-09-16 1994-04-12 靖仁 田中 Gimmick reel
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
WO2003067945A1 (en) * 2002-02-06 2003-08-14 Endress + Hauser Gmbh + Co. Kg Printed circuit board comprising a component

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