JPS5779628A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS5779628A
JPS5779628A JP55156358A JP15635880A JPS5779628A JP S5779628 A JPS5779628 A JP S5779628A JP 55156358 A JP55156358 A JP 55156358A JP 15635880 A JP15635880 A JP 15635880A JP S5779628 A JPS5779628 A JP S5779628A
Authority
JP
Japan
Prior art keywords
conductor
integrated circuit
contact
hybrid integrated
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55156358A
Other languages
Japanese (ja)
Inventor
Masahiro Otani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55156358A priority Critical patent/JPS5779628A/en
Publication of JPS5779628A publication Critical patent/JPS5779628A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent electric contact between a wire and a conductor, etc., of a hybrid integrated circuit by a method wherein the surface of the conductor or a resistor positioning under the bonding wire is covered with an insulating film. CONSTITUTION:The surface of the conductor 5 being in danger of coming in contact with the bonding wire 2 is covered preliminary with the insulating film 7, and formation of the insulating film thereof is performed by the screen printing method. Accordingly even when the bonding wire is made to come in contact with the conductor or the other material being unfavorable to contact, electric connection is not generated, and the high reliable hybrid integrated circuit can be obtained.
JP55156358A 1980-11-06 1980-11-06 Hybrid integrated circuit Pending JPS5779628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55156358A JPS5779628A (en) 1980-11-06 1980-11-06 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55156358A JPS5779628A (en) 1980-11-06 1980-11-06 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5779628A true JPS5779628A (en) 1982-05-18

Family

ID=15626006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55156358A Pending JPS5779628A (en) 1980-11-06 1980-11-06 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5779628A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61127139A (en) * 1984-11-24 1986-06-14 Rohm Co Ltd Semiconductor device
JPH01295430A (en) * 1988-05-24 1989-11-29 Matsushita Electric Works Ltd printed wiring board
US5229329A (en) * 1991-02-28 1993-07-20 Texas Instruments, Incorporated Method of manufacturing insulated lead frame for integrated circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61127139A (en) * 1984-11-24 1986-06-14 Rohm Co Ltd Semiconductor device
JPH01295430A (en) * 1988-05-24 1989-11-29 Matsushita Electric Works Ltd printed wiring board
US5229329A (en) * 1991-02-28 1993-07-20 Texas Instruments, Incorporated Method of manufacturing insulated lead frame for integrated circuits

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