JPS6489350A - Package for containing semiconductor element - Google Patents

Package for containing semiconductor element

Info

Publication number
JPS6489350A
JPS6489350A JP62247407A JP24740787A JPS6489350A JP S6489350 A JPS6489350 A JP S6489350A JP 62247407 A JP62247407 A JP 62247407A JP 24740787 A JP24740787 A JP 24740787A JP S6489350 A JPS6489350 A JP S6489350A
Authority
JP
Japan
Prior art keywords
semiconductor element
placing
layer
impregnated
gaps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247407A
Other languages
Japanese (ja)
Inventor
Hiroshi Toki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP62247407A priority Critical patent/JPS6489350A/en
Publication of JPS6489350A publication Critical patent/JPS6489350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To mount an insulating layer on a metal body rigidly with large electric insulation by employing a sintered porous material made of one or more types of W and Mo impregnated in its gaps with copper as the body for placing a semiconductor element. CONSTITUTION:A placing unit 1a for placing a semiconductor element 3 is provided at the center on the upper face of a metal body 1, and the element 3 is mounted on the unit 1a. The lower surface of the body 1 is covered with an insulating layer 1b. The body having the layer 1b on its lower surface is formed of a sintered porous material made of at least one type of W and Mo impregnated in its gaps with Cu. Thus, the layer 1b can be mounted on the body 1 rigidly with large electric insulation. As a result, when it is mounted on a circuit substrate, other electronic component and wiring lead are not brought into direct contact with the body 1, thereby operating the element 3 normally and stably for a long time.
JP62247407A 1987-09-29 1987-09-29 Package for containing semiconductor element Pending JPS6489350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247407A JPS6489350A (en) 1987-09-29 1987-09-29 Package for containing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247407A JPS6489350A (en) 1987-09-29 1987-09-29 Package for containing semiconductor element

Publications (1)

Publication Number Publication Date
JPS6489350A true JPS6489350A (en) 1989-04-03

Family

ID=17162975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247407A Pending JPS6489350A (en) 1987-09-29 1987-09-29 Package for containing semiconductor element

Country Status (1)

Country Link
JP (1) JPS6489350A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097318A (en) * 1988-04-04 1992-03-17 Hitachi, Ltd. Semiconductor package and computer using it
JPH0472639U (en) * 1990-10-31 1992-06-26
JPH05152469A (en) * 1991-11-28 1993-06-18 Kyocera Corp Semiconductor element storing package
US5798566A (en) * 1996-01-11 1998-08-25 Ngk Spark Plug Co., Ltd. Ceramic IC package base and ceramic cover
US5885853A (en) * 1990-06-22 1999-03-23 Digital Equipment Corporation Hollow chip package and method of manufacture
JP2003007891A (en) * 2001-06-26 2003-01-10 Kyocera Corp Package for storing semiconductor elements
US7180178B2 (en) * 2001-08-31 2007-02-20 Sumitomo Electric Industries, Ltd. Semiconductor heat-dissipating substrate, and manufacturing method and package therefor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097318A (en) * 1988-04-04 1992-03-17 Hitachi, Ltd. Semiconductor package and computer using it
US5885853A (en) * 1990-06-22 1999-03-23 Digital Equipment Corporation Hollow chip package and method of manufacture
JPH0472639U (en) * 1990-10-31 1992-06-26
JPH05152469A (en) * 1991-11-28 1993-06-18 Kyocera Corp Semiconductor element storing package
US5798566A (en) * 1996-01-11 1998-08-25 Ngk Spark Plug Co., Ltd. Ceramic IC package base and ceramic cover
JP2003007891A (en) * 2001-06-26 2003-01-10 Kyocera Corp Package for storing semiconductor elements
US7180178B2 (en) * 2001-08-31 2007-02-20 Sumitomo Electric Industries, Ltd. Semiconductor heat-dissipating substrate, and manufacturing method and package therefor

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