JPS5799754A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS5799754A
JPS5799754A JP55175293A JP17529380A JPS5799754A JP S5799754 A JPS5799754 A JP S5799754A JP 55175293 A JP55175293 A JP 55175293A JP 17529380 A JP17529380 A JP 17529380A JP S5799754 A JPS5799754 A JP S5799754A
Authority
JP
Japan
Prior art keywords
shaped
layer
sio2
poly
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55175293A
Other languages
Japanese (ja)
Other versions
JPS628025B2 (en
Inventor
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55175293A priority Critical patent/JPS5799754A/en
Priority to DE19813129558 priority patent/DE3129558A1/en
Publication of JPS5799754A publication Critical patent/JPS5799754A/en
Priority to US06/507,557 priority patent/US4507849A/en
Publication of JPS628025B2 publication Critical patent/JPS628025B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To separate an element by a method wherein a Si substrate, an uppmost layer thereof has a deposit layer of an n<+> layer, is separated by a V- shaped groove, the groove is buried completely with poly Si, n<+> diffusion is executed from the inside and the outside, and the n<+> layer is left in the V- shaped groove through selective etching. CONSTITUTION:SiO2 12, Si3N4 13 and PSG14 are stacked on a (911) surface of the Si substrate 11. The films 14-12 are opened to form the V-shaped grooves 15a, 15b and an island 15c. SiO2 16 is shaped at a high temperature under high pressure, and the grooves are buired with the poly Si. P is thermally diffused from the surface and the film 14, and n<+> layers 18, 19 are stacked. The layers 18, 19 are removed preferentially through a proper etching method, and poly Si 17a, 17b are left only in the grooves. The PSG14 is removed, SiO2 21 is shaped onto the layers 17a, 17b, the films 13, 12 are also removed, a pn junction is formed in the island 15c, and a desired device is shaped. According to this constitution, a flat minute element separation layer is obtained through a simple process.
JP55175293A 1980-07-28 1980-12-12 Manufacture of semiconductor integrated circuit Granted JPS5799754A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP55175293A JPS5799754A (en) 1980-12-12 1980-12-12 Manufacture of semiconductor integrated circuit
DE19813129558 DE3129558A1 (en) 1980-07-28 1981-07-27 METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR CIRCUIT
US06/507,557 US4507849A (en) 1980-07-28 1983-06-24 Method of making isolation grooves by over-filling with polycrystalline silicon having a difference in impurity concentration inside the grooves followed by etching off the overfill based upon this difference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175293A JPS5799754A (en) 1980-12-12 1980-12-12 Manufacture of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS5799754A true JPS5799754A (en) 1982-06-21
JPS628025B2 JPS628025B2 (en) 1987-02-20

Family

ID=15993575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175293A Granted JPS5799754A (en) 1980-07-28 1980-12-12 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5799754A (en)

Also Published As

Publication number Publication date
JPS628025B2 (en) 1987-02-20

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