JPS58114439A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS58114439A
JPS58114439A JP56209760A JP20976081A JPS58114439A JP S58114439 A JPS58114439 A JP S58114439A JP 56209760 A JP56209760 A JP 56209760A JP 20976081 A JP20976081 A JP 20976081A JP S58114439 A JPS58114439 A JP S58114439A
Authority
JP
Japan
Prior art keywords
single crystal
concave section
triangles
recess
poly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56209760A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0153509B2 (mo
Inventor
Hajime Kamioka
上岡　元
Mikio Takagi
幹夫 高木
Motoo Nakano
元雄 中野
Takashi Iwai
崇 岩井
Noriaki Sato
佐藤　典章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56209760A priority Critical patent/JPS58114439A/ja
Publication of JPS58114439A publication Critical patent/JPS58114439A/ja
Publication of JPH0153509B2 publication Critical patent/JPH0153509B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP56209760A 1981-12-28 1981-12-28 半導体装置の製造方法 Granted JPS58114439A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56209760A JPS58114439A (ja) 1981-12-28 1981-12-28 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56209760A JPS58114439A (ja) 1981-12-28 1981-12-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58114439A true JPS58114439A (ja) 1983-07-07
JPH0153509B2 JPH0153509B2 (mo) 1989-11-14

Family

ID=16578170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56209760A Granted JPS58114439A (ja) 1981-12-28 1981-12-28 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58114439A (mo)

Also Published As

Publication number Publication date
JPH0153509B2 (mo) 1989-11-14

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