JPS58115841A - 混成集積回路の製造方法 - Google Patents

混成集積回路の製造方法

Info

Publication number
JPS58115841A
JPS58115841A JP56211161A JP21116181A JPS58115841A JP S58115841 A JPS58115841 A JP S58115841A JP 56211161 A JP56211161 A JP 56211161A JP 21116181 A JP21116181 A JP 21116181A JP S58115841 A JPS58115841 A JP S58115841A
Authority
JP
Japan
Prior art keywords
pitch
lead frame
terminal
terminal pin
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56211161A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6352780B2 (2
Inventor
Yasumasa Fukushima
福島　康正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56211161A priority Critical patent/JPS58115841A/ja
Publication of JPS58115841A publication Critical patent/JPS58115841A/ja
Publication of JPS6352780B2 publication Critical patent/JPS6352780B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405—Edge mounted components, e.g. terminals

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP56211161A 1981-12-28 1981-12-28 混成集積回路の製造方法 Granted JPS58115841A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56211161A JPS58115841A (ja) 1981-12-28 1981-12-28 混成集積回路の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56211161A JPS58115841A (ja) 1981-12-28 1981-12-28 混成集積回路の製造方法

Publications (2)

Publication Number Publication Date
JPS58115841A true JPS58115841A (ja) 1983-07-09
JPS6352780B2 JPS6352780B2 (2) 1988-10-20

Family

ID=16601402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56211161A Granted JPS58115841A (ja) 1981-12-28 1981-12-28 混成集積回路の製造方法

Country Status (1)

Country Link
JP (1) JPS58115841A (2)

Also Published As

Publication number Publication date
JPS6352780B2 (2) 1988-10-20

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