JPS58123730A - Semiconductor wafer etching device - Google Patents

Semiconductor wafer etching device

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Publication number
JPS58123730A
JPS58123730A JP567082A JP567082A JPS58123730A JP S58123730 A JPS58123730 A JP S58123730A JP 567082 A JP567082 A JP 567082A JP 567082 A JP567082 A JP 567082A JP S58123730 A JPS58123730 A JP S58123730A
Authority
JP
Japan
Prior art keywords
etching
semiconductor wafer
etching liquid
prescribed
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP567082A
Other languages
Japanese (ja)
Inventor
Yasushi Yanagida
柳田 寧
Makoto Imagawa
誠 今川
Toshio Yoneda
敏雄 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP567082A priority Critical patent/JPS58123730A/en
Publication of JPS58123730A publication Critical patent/JPS58123730A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To perform the etching uniformly and in high degree of accuracy by a method wherein a temperature controller for etching liquid and a bubble generator, with which bubbles are generated in the etching liquid, are provided. CONSTITUTION:The etching liquid of the prescribed quantity is filled in a vessel 3, and the prescribed temperature is set by a temperature controller 7. The prescribed number of semiconductor wafers 11 are supported by a supporting part 9a in the state of condition wherein a great number of bubbles, generated by a bubble generator 8, are existing in the etching liquid, and an etching work is performed. Then, after said etching work has been finished, a pinching frame 9b is moved to a cleaning vessel 4 using an electric controller 10, and a cleaning work is performed there. In synchronizing with the above, the temperature inside an etching vessel 3 is set at the prescribed value by adjusting a thermostat 7a. Subsequently, new semiconductor wafer 11 is placed on the supporting part 9a, and a desired etching process is performed by repeating the above operation in the same manner.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、半導体ウェハーエツチング装置に関する。[Detailed description of the invention] Technical field of invention The present invention relates to a semiconductor wafer etching apparatus.

発明の技術的背景と、その問題点 従来、半導体ウェハーエツチング装置は、半導体ウェハ
をエツチング液中に浸漬して回転子で回転させな−から
エツチング処理を施すか、或は、半導体ウェハに直接上
下運動を施して揺動させながら、工、チング処理を施す
構造になっている。しかしながら、このような構造の半
導体ウェハーエツチング装置で拡、半導体ウェハーを支
持する治具の形状によってエツチング処理の度合が左右
され、均一な工、チング処理を施すことが困難である。
Technical background of the invention and its problems Conventionally, semiconductor wafer etching equipment has either dipped the semiconductor wafer in an etching solution and performed the etching process without rotating it with a rotor, or directly etched the semiconductor wafer up and down. The structure is such that it can be moved and swung while being subjected to machining and chiming processes. However, in a semiconductor wafer etching apparatus having such a structure, the degree of etching depends on the shape of the jig that supports the semiconductor wafer, making it difficult to perform uniform etching.

41に、半導体ウェハーK10μm以上のエツチング処
理を施す場合には、この欠点が顕著に現われる。また、
エツチング液を霧状にして半導体ウェハーに吹付けるよ
5うにした構造の半導体ウェハーエツチング装置が開発
されている。この半導体ウェハーエツチング装置では、
極めて均一な度合でエツチング処理を施すことができる
が、エツチング液の回収が困難であシ、経済性に乏しく
量産性が低い欠点がある。
When etching a semiconductor wafer K of 10 μm or more to 41, this drawback becomes noticeable. Also,
A semiconductor wafer etching apparatus has been developed in which a mist of etching solution is sprayed onto the semiconductor wafer. In this semiconductor wafer etching equipment,
Although the etching process can be carried out with an extremely uniform degree, it is difficult to recover the etching solution, and has the drawbacks of poor economic efficiency and low mass production.

発明の目的 本発明は、極めて均一なエツチング処理を高い精度で施
すことができ、しかも工、チング量の制御が容易である
半導体ウェハーエ、チング装置を提供することをその目
的とするものである。
OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor wafer etching apparatus which can perform extremely uniform etching with high accuracy and can easily control the amount of etching.

見間の概要 本発明は、エツチング液の温度制御器と工。Overview of Mima The present invention relates to an etching solution temperature controller and process.

チンダ液中に気泡を発生せしめる気泡発生器とを設けた
ことにより、高い精度で均一なエツチング処理を施すこ
とができ、しかも、エツチング量の制御を容易にした半
導体ウェハーエツチング装置である。
This semiconductor wafer etching apparatus is equipped with a bubble generator that generates bubbles in the tinting liquid, so that uniform etching can be performed with high precision, and the amount of etching can be easily controlled.

発明の実施例 第1図は、本発明の一実施例の概略構成を示す説明図で
ある。図中1は、エツチング装置本体である。エツチン
グ装置本体1は、仕切板2を介してエツチング槽3と洗
浄槽4に仕切られている。洗浄槽4の下方には、エツチ
ング装置本体1の底部を貫挿して洗浄水供給管5&と洗
浄水排出管5kが設けられている。工、チング槽3の下
方には、エツチング装置本体1の底部金員挿してエツチ
ング液供給管6&とエツチング液還流管6bが設けられ
ている。工、チング液供給管6a及びエツチング液還流
管6bは、冷却器、熱交換器、エツチング液還流モータ
、エツチング液温センナなどを含む恒温設定機構raを
内蔵したエツチング液温度制御装置1に接続されている
。エツチング槽3の底部には、気泡発生器Iが設置され
ている。気泡発生器8は、第2図に示す如く、耐酸性の
合成轡脂からなる上部を開口した気泡発生箱#aの側部
に、エツチング装置本体1の外部から気泡発11スこの
蓋体8シを押え板8@で固定した構造を有している。蓋
体8d及び押え板8・は、エツチング液に侵されないフ
ッ素系の樹脂で形成されている1、発泡孔8cは、気泡
発生ガス供給w8bから供給された気泡発生ガスをエツ
チング液中に放出することによ″′シ発泡を発生せしめ
るもので′h)、その径を約200pln以下に設定す
るのが望ましい、tた、蓋体8dの大きさは、エツチン
グ処理を施す半導体クエハ(後述する)の径及び処理枚
数に応じて適宜設定するのが好ましい。例えば、半導体
ウニへの径が2〜4インチで処理枚数が50〜100枚
の場合には、蓋体ad(Q縦を80〜100■、横を2
50〜300■に設定するのが望ましい。
Embodiment of the Invention FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the invention. 1 in the figure is the main body of the etching apparatus. The etching apparatus main body 1 is partitioned into an etching tank 3 and a cleaning tank 4 via a partition plate 2. Below the cleaning tank 4, a cleaning water supply pipe 5& and a cleaning water discharge pipe 5k are provided, penetrating the bottom of the etching apparatus main body 1. An etching liquid supply pipe 6& and an etching liquid return pipe 6b are provided below the etching tank 3 by inserting them into the bottom metal fittings of the etching apparatus main body 1. The etching liquid supply pipe 6a and the etching liquid return pipe 6b are connected to an etching liquid temperature control device 1 having a built-in constant temperature setting mechanism RA including a cooler, a heat exchanger, an etching liquid return motor, an etching liquid temperature sensor, etc. ing. At the bottom of the etching tank 3, a bubble generator I is installed. As shown in FIG. 2, the bubble generator 8 generates bubbles 11 from the outside of the etching apparatus body 1 into the side of a bubble generating box #a made of acid-resistant synthetic resin and having an open top. It has a structure in which the holder is fixed with a presser plate 8@. The lid 8d and the presser plate 8 are made of a fluorine-based resin that is not corroded by the etching solution.The foaming hole 8c releases the bubble-generating gas supplied from the bubble-generating gas supply w8b into the etching solution. It is preferable to set the diameter to about 200 pln or less, as it may cause foaming in some cases.In addition, the size of the lid 8d is determined by the size of the semiconductor wafer to be etched (described later). It is preferable to set the appropriate setting according to the diameter of the semiconductor urchin and the number of sheets to be processed.For example, when the diameter of the semiconductor sea urchin is 2 to 4 inches and the number of sheets to be processed is 50 to 100, the lid ad (Q length is 80 to 100 ■, side 2
It is desirable to set it to 50-300■.

を九、エツチング槽a内には、駆動モータ、駆動制御機
器を含む駆動部SO半導体会エノ・保持部9aが出入自
在に収容されている。駆動部9は、半導体ウェハ保持部
9a−を挾持した挟持枠9bと、)、りg−を介して挾
持枠#bが吊下されたアームガイド9纏と、駆動部9に
電気的に接続され、挾持枠#bを7−ムガイ1」にGq
て移動せしめる電気制御部10とで構成されている。こ
の電気制御部1#ではエツチング液温及び駆動モードが
電気的に設定され制御されている。なお、アームガイド
g4は、工。
9. Inside the etching bath a, a drive unit SO semiconductor industry/holding unit 9a including a drive motor and drive control equipment is housed so as to be freely accessible and removable. The drive unit 9 is electrically connected to the drive unit 9, a clamping frame 9b that clamps the semiconductor wafer holding unit 9a-, an arm guide 9 from which the clamping frame #b is suspended via a and Gq the holding frame #b to 7-mugai 1.
It is composed of an electric control section 10 that allows movement. In this electric control section 1#, the etching liquid temperature and drive mode are electrically set and controlled. In addition, the arm guide g4 is manufactured by engineering.

チング装置本体1の上方に、エツチング槽3と洗浄槽4
に跨がるように形成されている。また、半導体クエハ保
持部9aは、対向する保持板9a1の内面に、被工、チ
ンダ体である半導体つ、、l−11の周縁部を保持する
溝を複数本所定間隔を設けて形成し、50〜100枚の
半導体ウニへ11を保持するようになっている。電気制
御部10は、エツチング液温度制御装置1の恒温設定機
構11に電気的に接続されており、挟持枠Jkの移動に
連動して恒温設定機構1aによシエ、チング槽3内のエ
ツチング液の温度を所定温度に設定するようになってい
る。
An etching tank 3 and a cleaning tank 4 are installed above the etching device main body 1.
It is formed to straddle the . In addition, the semiconductor wafer holding portion 9a has a plurality of grooves formed at predetermined intervals on the inner surface of the opposing holding plate 9a1 to hold the peripheral edge portions of the semiconductor wafers 1-11, which are workpieces and chipped bodies. It is designed to hold 11 to 50 to 100 semiconductor urchins. The electric control unit 10 is electrically connected to the constant temperature setting mechanism 11 of the etching liquid temperature control device 1, and controls the constant temperature setting mechanism 1a in conjunction with the movement of the holding frame Jk, thereby controlling the etching liquid in the etching tank 3. temperature is set to a predetermined temperature.

エツチング槽3内には、エツチング液供給管6aからエ
ツチング液を供給し、オー・童フローしたエツチング液
をエツチング液還流管6bによシ回収することにより、
常に一定量のエツチング液が満されるようになりている
。また、洗浄槽4内には、洗浄水供給管5aから洗浄水
が供給され、オーツ々フローした洗浄水を洗浄水排出管
5bから回収することによシ、常に一定量の洗浄水が満
されるようKなっている。なお、洗浄槽4内ニ、エツチ
ング処理の施された半導体ウエノ・11を回転せしめる
回転子や気泡−生器岬を設けて、エツチング処理により
て半導体ウェノ・11の表面に付着した酸の除去を促進
するようにしても良い。
Etching liquid is supplied into the etching tank 3 from the etching liquid supply pipe 6a, and the etching liquid that has flowed out is recovered through the etching liquid return pipe 6b.
A certain amount of etching solution is always filled. In addition, washing water is supplied into the washing tank 4 from a washing water supply pipe 5a, and by collecting the washing water that flows out from the washing water discharge pipe 5b, a certain amount of washing water is always filled. It is set as K. Furthermore, inside the cleaning tank 4, a rotor for rotating the etched semiconductor wafer 11 and a bubble cape are provided to remove the acid attached to the surface of the semiconductor wafer 11 during the etching process. It may also be promoted.

而して、このように構成され九半導体つェノ1−エツチ
ング装置LAによれば、エツチング槽3内に所定量溝さ
れた工、チンダ液をエツチング液温度制御装置1により
所定温度に設定し、かつ、気泡発生器1によって工、チ
ンダ液中に多数個の気泡を発生させた状態で、半導体ウ
ェハ保持部pmに所定枚数の半導体クエへ11を保持さ
せた状態でエツチング槽3中に浸漬し、工、チング処理
を施す1次いで、電気制御部10によりエツチング処理
後に挾持枠#bを洗浄槽4に移し、半導体ウェハ11を
洗浄すると共に、これと同期して電気制御部10C)指
令に基づいて恒温設定機構7aを調節して、工、チング
槽3内の温度を所定温度に設定する。然る後、保持部9
aに新しい半導体ウェハ、11を塔載し、同様の操作を
繰)返して毛簿体つェ八11に所望の工、チンダ処理を
施す。その結果、次のような効果を有する。
According to the semiconductor etcher LA constructed in this manner, the temperature of the etching solution is set to a predetermined temperature by the etching solution temperature control device 1. , and with a large number of bubbles generated in the etching solution by the bubble generator 1, a predetermined number of semiconductor wafers 11 are held in the semiconductor wafer holder pm and immersed in the etching bath 3. Then, after the etching process, the electric control unit 10 transfers the holding frame #b to the cleaning tank 4 and cleans the semiconductor wafer 11. At the same time, the electric control unit 10C) Based on this, the constant temperature setting mechanism 7a is adjusted to set the temperature inside the heating tank 3 to a predetermined temperature. After that, the holding part 9
A new semiconductor wafer 11 is placed on top of a, and the same operation is repeated to apply the desired finishing and tinting treatment to the substrate wafer 11. As a result, the following effects are achieved.

■ エツチング量のばらつきは、半導体ウニへ11の厚
さに対して±1μmに設定できる、。
■ The variation in the amount of etching can be set to ±1 μm for the thickness of the semiconductor layer 11.

(従来の装置では、±5μmOばらつキ量であった。) ■ 工、チング処理抜の平行度は、第4図に曲線(1)
で示す如く、実施例のものでは同図中曲線ω)で示す従
来の装置に比べて半導体ウェハ11(D中心部の厚さと
の差を5〜6分の1に減少できる。
(With the conventional device, the variation was ±5μmO.) ■ The parallelism without machining and ching is shown in curve (1) in Figure 4.
As shown in FIG. 2, the difference in thickness of the semiconductor wafer 11 (D) can be reduced to one-fifth to one-sixth of that of the conventional device shown by the curve ω) in the figure.

■ エツチング処理後の仕上げ面の鏡面度が、従来の装
置による場合に比べて遥かに機械研摩品の鏡面度に近づ
き、工、チンダ液の寿命が約1.5倍になる。
- The specularity of the finished surface after etching is much closer to the specularity of mechanically polished products than when using conventional equipment, and the life of the etching solution is approximately 1.5 times longer.

■ 半導体クエへ11を保持する半導体ウェハ保持部9
aの形状によってエツチング量が左右されないので、既
製のキャリアを半導体つ8−、&□9.に□11111
□fbjhヵ8□4゜■ 1回の工、チンダ処理に要す
る処理時間を短縮して生産性を向上させることができる
■ Semiconductor wafer holding section 9 that holds semiconductor wafer 11
Since the amount of etching is not affected by the shape of a, ready-made carriers can be used for semiconductors 8-, & 9. ni□11111
□fbjhka8□4゜■ It is possible to improve productivity by shortening the processing time required for one-time machining and tinkering.

発明の詳細 な説明した如く、本発明に係る半導体ウェハーエ、チン
ダ装置によれば、極めて均一なエツチング処理を高い精
度で施すことができ、しかもエツチング量の制御が容易
である尋顕著な効果を奏するもOである。
As described in detail, the semiconductor wafer etching apparatus of the present invention can perform extremely uniform etching with high accuracy, and the amount of etching can be easily controlled, which is a remarkable effect. is also O.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例O概略構成を示す説明図、
第2図は、気泡発生器t)ltl1図、第3図は、同気
泡発生器の蓋体O斜視図、第4図は、半導体ウェハの中
心、部における肉厚との差と外周からの距離の関係を示
す特性図である。 、1・・・工、チンダ装置本体、2−・仕切板、3・・
・工、チング槽、4・・・洗浄槽、j6−・洗浄水供給
管、sb・・・洗浄水排出管、ga・・・工、チンダ液
供給管、6b・・・エツチング液還流管、1・・・エツ
チング液温度制御装置、7 m ・・・恒温設定機構、
8・・・気泡発生器、8a・・・気泡発生箱、8b・・
・気泡発生ガス供給管、Je・・・発泡孔、am・・・
蓋体、8・・・・押え板、9・・・駆動部、ta・・・
半導体ウェハ保持部、9b・・・挟持部、りC・・・フ
ック、9d・・・アームガイド、10・・・電気制御部
、11・・・半導体クエ/\、L」・・・半導体ウエノ
・−エツチング装置。
FIG. 1 is an explanatory diagram showing the schematic configuration of an embodiment of the present invention;
Fig. 2 is a diagram of the bubble generator, Fig. 3 is a perspective view of the lid O of the bubble generator, and Fig. 4 is a diagram showing the difference in wall thickness at the center of the semiconductor wafer and the difference in thickness from the outer periphery. FIG. 3 is a characteristic diagram showing the relationship between distances. , 1...work, cinder device main body, 2--partition plate, 3...
- Engineering, etching tank, 4... Cleaning tank, j6 - Washing water supply pipe, sb... Washing water discharge pipe, ga... Engineering, Chinda liquid supply pipe, 6b... Etching liquid return pipe, 1... Etching liquid temperature control device, 7 m... Constant temperature setting mechanism,
8...Bubble generator, 8a...Bubble generating box, 8b...
・Bubble-generating gas supply pipe, Je... foaming hole, am...
Lid body, 8...pressing plate, 9...driver, ta...
Semiconductor wafer holding part, 9b... Holding part, C... Hook, 9d... Arm guide, 10... Electrical control part, 11... Semiconductor que/\, L"... Semiconductor wafer・-Etching device.

Claims (1)

【特許請求の範囲】 エツチング槽内に設けられた気泡発生器と、前記工、チ
ング槽に工、チンダ液供給管及び工、チンダ液還流管を
介して接続し、がっ、恒温設定機構を内蔵し九温度制御
器と、被エッチン4グ体保持部を有し、かつ、該保持部
を前記工。 チング槽内に出入せしめる駆動部を備え九被工、チング
体保持機構とを具備することを4IgLとする半導体ウ
ェハーエツチング装置。
[Claims] A bubble generator provided in the etching tank is connected to the etching tank via a tinda liquid supply pipe and a tinda liquid return pipe, and a constant temperature setting mechanism is provided. It has a built-in temperature controller and a holding part for the object to be etched, and the holding part is used for the above-mentioned process. 4. A semiconductor wafer etching apparatus which is equipped with a drive unit for moving the etching body into and out of the etching bath, a nine-workpiece, and a etching body holding mechanism.
JP567082A 1982-01-18 1982-01-18 Semiconductor wafer etching device Pending JPS58123730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP567082A JPS58123730A (en) 1982-01-18 1982-01-18 Semiconductor wafer etching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP567082A JPS58123730A (en) 1982-01-18 1982-01-18 Semiconductor wafer etching device

Publications (1)

Publication Number Publication Date
JPS58123730A true JPS58123730A (en) 1983-07-23

Family

ID=11617532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP567082A Pending JPS58123730A (en) 1982-01-18 1982-01-18 Semiconductor wafer etching device

Country Status (1)

Country Link
JP (1) JPS58123730A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6183033U (en) * 1984-11-06 1986-06-02
JPS6386525A (en) * 1986-09-30 1988-04-16 Kyushu Denshi Kinzoku Kk Device for etching semiconductor silicon wafer
US5159946A (en) * 1989-05-15 1992-11-03 Aigo Seiichiro Over-flow tank for a semiconductor wafer washing apparatus
US5839456A (en) * 1996-12-24 1998-11-24 Lg Semicon Co., Ltd. Wafer wet treating apparatus
CN111524834A (en) * 2020-04-29 2020-08-11 西安奕斯伟硅片技术有限公司 A polysilicon cleaning device and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5568633A (en) * 1978-11-20 1980-05-23 Fujitsu Ltd Method and device for back etching of semiconductor substrate
JPS5617021A (en) * 1979-07-20 1981-02-18 Fujitsu Ltd Surface treatment of substrate
JPS56120132A (en) * 1980-02-27 1981-09-21 Hitachi Ltd Wafer etching method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5568633A (en) * 1978-11-20 1980-05-23 Fujitsu Ltd Method and device for back etching of semiconductor substrate
JPS5617021A (en) * 1979-07-20 1981-02-18 Fujitsu Ltd Surface treatment of substrate
JPS56120132A (en) * 1980-02-27 1981-09-21 Hitachi Ltd Wafer etching method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6183033U (en) * 1984-11-06 1986-06-02
JPS6386525A (en) * 1986-09-30 1988-04-16 Kyushu Denshi Kinzoku Kk Device for etching semiconductor silicon wafer
US5159946A (en) * 1989-05-15 1992-11-03 Aigo Seiichiro Over-flow tank for a semiconductor wafer washing apparatus
US5839456A (en) * 1996-12-24 1998-11-24 Lg Semicon Co., Ltd. Wafer wet treating apparatus
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