JPS58140A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS58140A
JPS58140A JP56098545A JP9854581A JPS58140A JP S58140 A JPS58140 A JP S58140A JP 56098545 A JP56098545 A JP 56098545A JP 9854581 A JP9854581 A JP 9854581A JP S58140 A JPS58140 A JP S58140A
Authority
JP
Japan
Prior art keywords
patterns
wiring
conductor
insulating film
recognition pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56098545A
Other languages
Japanese (ja)
Inventor
Eiji Miyajima
宮嶋　栄志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56098545A priority Critical patent/JPS58140A/en
Publication of JPS58140A publication Critical patent/JPS58140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate formation by shaping a recognition pattern for wire bonding onto a wiring conductor or an insulating film formed to a concave section molded by the wiring conductor. CONSTITUTION:When the recognition patterns 10 consisting of conductor films are shaped onto the wiring conductors 7 on a ceramic substrate 6, the concave sections among the wiring conductors 7 are burined with black crystallized glass 8, black crystallized glass 9 is further stacked and the patterns 10 are formed. Accordingly, the surfaces of the patterns 10 are flattened, the diffused reflection of beams is not generated, and the minute patterns can easily by shaped.

Description

【発明の詳細な説明】 本発明は基板上に全自動ワイヤーボンディング用ｍＩｌ
パターンを備えた厚膜形成等からなるハイブリッドＩＣ
に関する・ ハイブリッドエＣにおいては通常セラミック等からなる
基板上に半導体素子等の個別部品が実装されており、該
個別部品と基板上に配線された導体パターン間や導体パ
ターン相互間等をワイヤーボンディング接続して製造さ
れている。このワイヤーボンディング手段として近時全
自動のものが実用化されてお）、これは基板上に配縁導
体と同様な導体膜からなる膜認識パターン【予じめ少な
くとも２個形成しておき、ボンディング時にはこの認識
パターンに光を照射してその反射光を受光部で検知する
ことにより認識パターンの位置を検出し、それにより自
動位置補正を行ないワイヤーボンディングするもので参
る・ ところで、従来では光学的に明暗を得る認識パターン構
造として第１図の４ｈのが実施されてい友。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a mold for fully automatic wire bonding on a substrate.
Hybrid IC consisting of thick film formation with pattern, etc.
- In Hybrid E-C, individual components such as semiconductor elements are mounted on a substrate usually made of ceramic etc., and wire bonding is used to connect the individual components and conductor patterns wired on the substrate or between conductor patterns. It is manufactured by Recently, a fully automatic wire bonding method has been put into practical use), and this method involves forming at least two film recognition patterns (previously formed on the substrate) consisting of a conductor film similar to the wiring conductor, and bonding. Sometimes, the position of the recognition pattern is detected by irradiating light onto this recognition pattern and detecting the reflected light with a light receiving section, and then automatically correcting the position and wire bonding. 4h in Figure 1 has been implemented as a recognition pattern structure for obtaining brightness and darkness.

第１図において、１はセラ建ツク基板％２は絶縁膜であ
る黒色結晶化ガラス膜、３は導体膜からなる認識パター
ン、４はワイヤーボンディングされる配−導体、δはボ
ンディンダワイヤーである。In Fig. 1, 1 is a ceramic building board, 2 is a black crystallized glass film which is an insulating film, 3 is a recognition pattern consisting of a conductor film, 4 is a wiring conductor to be wire bonded, and δ is a bonder wire. .

すなわち、従来においては光を反射させる認識パターン
３としてはその表面が光の乱反射を生じないように平坦
である必要性がある丸め、基板１のあきスペースに形成
してお）高密ｆＫ配線導体４が設けられ九へイブリッド
エ０には適用できない欠点があり九〇 本発明はこの従来欠点を解決したもので、以下第３１図
により実施真倉説明する。That is, in the past, the recognition pattern 3 for reflecting light was formed in a rounded shape whose surface needed to be flat so as not to cause diffuse reflection of light, and was formed in an open space on the board 1). The present invention solves this conventional drawback and will be explained below with reference to FIG. 31.

第２図において、６は竜ラミック基板、マは高ｍ度に配
−され九配線導体、８は配線導体１の隣接間に生じる凹
部を堀める黒色結晶化ガラス膜からなる第１の絶縁膜、
９は黒色結晶化ガラス膜からなる第２の絶縁膜、１０は
導体膜からなる認識パターン、１１はボンディングワイ
ヤである。本ハイブリッドＩＯにおいては認識パターン
１０が配線導体グ上に形成されである点で第１図の従来
と真なり、且つ配線導体１上へのｇＩｌパターン１０形
成を可１とにさせるため本ハイブリッドＩＣでは第２絶
縁膜９の下に隣接配線導体１間に生じる凹部を埋める＠
１絶ｌ１ｋ１１Ｂが設けられており認識パター７１０表
（３）の平坦化が実現されている。In Fig. 2, numeral 6 denotes a lamic substrate, numeral numeral 9 conductors arranged at a high degree, and numeral 8 a first insulator made of a black crystallized glass film that digs the recesses formed between adjacent wiring conductors 1. film,
9 is a second insulating film made of a black crystallized glass film, 10 is a recognition pattern made of a conductive film, and 11 is a bonding wire. In this hybrid IO, the recognition pattern 10 is formed on the wiring conductor 1, which is true of the conventional example shown in FIG. Now, fill in the recesses created between the adjacent wiring conductors 1 under the second insulating film 9.
11k11B is provided, and flattening of the recognition pattern 710 table (3) is realized.

以上の本祐明によれば、高密直配−のハイブリッドＩＯ
４全自動ワイヤボンディングの適用が可能になり、且つ
その認識パターン構造４安価で且つ容易に実施できるな
ど実用上の効果は著しいものである。According to Yuaki Moto mentioned above, hybrid IO with high-density direct distribution
4 Fully automatic wire bonding can be applied, and the recognition pattern structure 4 can be implemented inexpensively and easily, resulting in remarkable practical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のハイブリッドＩＣｔ−示す側断面図、第
３図線本発明に傷みハイブリッドＸａ（示す側断面図で
おる。 〔符号の説明〕 ６・・・・・・・・基　　板 フ・・・・・・・・・配−導体 ８．９・・・・・・・・・絶縁膜 １０・・・・・・・・・認識パターン １１・・・・・・・・・ボンディンダワイヤ代理人　弁
理士　松　岡　宏四部゛Fig. 1 is a side sectional view showing a conventional hybrid ICt, and Fig. 3 is a side sectional view showing a damaged hybrid Xa according to the present invention. ...... Wiring conductor 8.9 ...... Insulating film 10 ...... Recognition pattern 11 ...... Bondinder wire Agent Patent Attorney Hiroshi Matsuoka

Claims (2)

【特許請求の範囲】[Claims] （１）　　全自動ワイヤーボンディング用認識パターン
會配線導体上に絶縁膜を介して設けたことを特徴とした
ハイブリッドエ００(1) Hybrid E00, which is characterized by a recognition pattern for fully automatic wire bonding, which is provided on the wiring conductor via an insulating film. （２）　　前記絶縁膜は前記配線導体により生じている
凹Ｓｔ埋める絶縁膜上に設けられていることｔ籍値とじ
九特許請求の範凹第１項記載のハイブリッドＩＣ(2) The insulating film is provided on an insulating film that fills the recesses formed by the wiring conductors.
JP56098545A 1981-06-25 1981-06-25 Hybrid integrated circuit Pending JPS58140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56098545A JPS58140A (en) 1981-06-25 1981-06-25 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56098545A JPS58140A (en) 1981-06-25 1981-06-25 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58140A true JPS58140A (en) 1983-01-05

Family

ID=14222652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56098545A Pending JPS58140A (en) 1981-06-25 1981-06-25 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58140A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4929500A (en) * 1986-04-03 1990-05-29 Komag, Inc. Corrosion resistant magnetic disk
JPH0716140A (en) * 1992-06-19 1995-01-20 Hajime Okaji Clothes hanger
US20170373102A1 (en) * 2015-04-23 2017-12-28 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display panel and display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4810854U (en) * 1971-06-17 1973-02-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4810854U (en) * 1971-06-17 1973-02-07

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4929500A (en) * 1986-04-03 1990-05-29 Komag, Inc. Corrosion resistant magnetic disk
JPH0716140A (en) * 1992-06-19 1995-01-20 Hajime Okaji Clothes hanger
US20170373102A1 (en) * 2015-04-23 2017-12-28 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display panel and display device
US10192907B2 (en) * 2015-04-23 2019-01-29 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display panel and display device

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