JPS58142575A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS58142575A
JPS58142575A JP57026247A JP2624782A JPS58142575A JP S58142575 A JPS58142575 A JP S58142575A JP 57026247 A JP57026247 A JP 57026247A JP 2624782 A JP2624782 A JP 2624782A JP S58142575 A JPS58142575 A JP S58142575A
Authority
JP
Japan
Prior art keywords
emitter
layer
film
mask
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57026247A
Other languages
Japanese (ja)
Inventor
Tsutomu Fujita
勉 藤田
Toyoki Takemoto
竹本 豊樹
Hiroyuki Sakai
坂井 弘之
Kenji Kawakita
川北 憲司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57026247A priority Critical patent/JPS58142575A/en
Publication of JPS58142575A publication Critical patent/JPS58142575A/en
Priority to US06/660,255 priority patent/US4563227A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a high density and high speed bipolar transistor by executing selective oxidation after etching the Si layer with the oxidation resistant film used as the mask and by providing the emitter with the side placed in contact with almost vertically formed isolation oxide film. CONSTITUTION:After the N type epitaxial layer 35 and SiO2 36 on the P type Si substrate having the N<+> type buried layer are vertically etched by the reactive sputtering method using Si3N4 layer as the mask 37, the SiO2 39 and Si3N4 40 are stacked on the N layer 35. These are vertically etched and left at the side. When an insulating isolation film 41 is formed in contact with the buried layer by oxidation, a bird's beak is not generated thanks to the film 40. An opening is provided on the mask 37 and thereby the SiO2 film 42 is formed and the P layer 43 is selectively formed. The surface is covered with the poly-Si 44, the Si3N4 mask 45 is provided and an opening is provided on the film 44, the P layer 43 is etched in the shallow depth, the surface is covered with the SiO2 46, the mask 45 is removed, ion is implanted selectively, and the N emitter 47, collector connecting layer 48, and inactive base 48 are sequentially formed and the electrodes are attached. According to this structure, there is no bird's beak, parasitic capacitance at the side of emitter and a high density and high speed device can be obtained.

Description

【発明の詳細な説明】 本発明は絶縁分離形バイポーラトランジスタを含む半導
体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device including an isolation type bipolar transistor.

バイポーラトランジスタにおいても、MoSトランジス
タと同様に高密度化が進んでいる。その方法としてはト
ランジスタのサイズを非常に小さくできる絶縁分離がよ
く用いられる0この絶縁分離は活性領域となる部分のみ
にSi3H4等の耐酸化膜を被覆して酸化膜を形成する
いわゆるLOCO8法がよく知られている。
Bipolar transistors are also becoming denser, similar to MoS transistors. As a method for this purpose, insulation isolation is often used because it can make the size of the transistor extremely small.The so-called LOCO8 method is often used for this insulation isolation, in which an oxidation-resistant film such as Si3H4 is coated only on the part that will become the active region. Are known.

しかしながら、このLOCO8法は酸化膜が活性領域へ
侵入するバーズビークを生じる欠点を有する。このバー
ズビークのあるLOCO8法の例を第1図に示す。第1
図において、1は厚い酸化膜で分離領域となる。2はバ
ーズビークで島領域中に島のくちばしのようにのびてい
る03ばn+埋込層、4はp型基板、5はコレクタ領域
、6はベースとコレクタコンタクトを分ける酸化膜、7
はベース8とエミッタ9を分離する酸化膜である。
However, this LOCO8 method has the drawback of creating a bird's beak where the oxide film invades the active region. An example of the LOCO8 method with bird's beak is shown in FIG. 1st
In the figure, 1 is a thick oxide film and serves as an isolation region. 2 is a bird's beak extending into the island region like the beak of the island; 03B n+ buried layer; 4 is a p-type substrate; 5 is a collector region; 6 is an oxide film separating the base and collector contact; 7
is an oxide film separating the base 8 and emitter 9.

第1図のごとく、バーズビーク2の生じた絶縁物1によ
って分離された島領域にバイポーラトランジスタを形成
すると以下に述べる欠点を有する。
As shown in FIG. 1, if a bipolar transistor is formed in an island region separated by an insulator 1 where a bird's beak 2 is formed, there will be the following drawbacks.

即ち、分離領域1に接してエミッタ9を形成しても分離
領域1の側面形状が基板4に対して垂直になっていない
ので、エミッタ9の側面はほとんど酸化膜1によって被
覆されることがない。この為エミッタ9の側面は直接ベ
ース8と接するので、エミッタ・ベース間の容量が大き
くなる。さらにエミッタ9の側面は酸化膜1で被覆され
ないので、エミツタ9形成時の横方向広がりの形状がそ
のままのこり、その結果エミッタ9のエツジ部は楕円形
状を有することになる。この結果、エミツタ9中央部に
比べてエミッタ9周辺部のベース幅が広くなり高周波特
性の劣化を生じ、同時に、トランジスタの亀流増1唱率
も下がることになる。このように、バーズビークの生じ
ている絶縁分離領域に接してエミッタが形成されたバイ
ポーラトランジスタは種々の欠点を有する。
That is, even if the emitter 9 is formed in contact with the isolation region 1, the side surface of the isolation region 1 is not perpendicular to the substrate 4, so the side surface of the emitter 9 is hardly covered with the oxide film 1. . Therefore, the side surface of the emitter 9 is in direct contact with the base 8, so that the capacitance between the emitter and the base becomes large. Furthermore, since the side surfaces of the emitter 9 are not covered with the oxide film 1, the shape of the emitter 9 which is spread in the lateral direction when it is formed remains unchanged, and as a result, the edge portion of the emitter 9 has an elliptical shape. As a result, the base width at the periphery of the emitter 9 becomes wider than at the center of the emitter 9, resulting in deterioration of the high frequency characteristics, and at the same time, the transistor current increase rate also decreases. As described above, a bipolar transistor in which an emitter is formed in contact with an isolation region where a bird's beak occurs has various drawbacks.

以上述べた欠点に鑑み、本発明は高周波特性がよくかつ
電流増幅率が劣化しない絶縁分離形バイポーラトランジ
スタを含む箪導体装置の製造法を提供するものである。
In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a rectangular conductor device including an isolated bipolar transistor having good high frequency characteristics and no deterioration in current amplification factor.

以下、本発明の構成を実施例をもとに詳細に説明する。Hereinafter, the configuration of the present invention will be explained in detail based on examples.

第2図aは本発明に係る製造方法により形成されたバイ
ポーラトランジスタの構造断面図で、第2図すはその平
面図である。第2図において、21は厚い素子間分離酸
化膜、22は酸化膜21の端部、23はn+埋込層、2
4はp型基板、26はn形コレクタ、26はコレクター
ベース間分離酸化膜、27はベース−エミッタ間分離酸
化膜、28はベース、29はエミッタ、3oはコレクタ
25のコンタクト部分を示す。
FIG. 2A is a cross-sectional view of the structure of a bipolar transistor formed by the manufacturing method according to the present invention, and FIG. 2A is a plan view thereof. In FIG. 2, 21 is a thick element isolation oxide film, 22 is an end of the oxide film 21, 23 is an n+ buried layer, 2
4 is a p-type substrate, 26 is an n-type collector, 26 is a collector-base isolation oxide film, 27 is a base-emitter isolation oxide film, 28 is a base, 29 is an emitter, and 3o is a contact portion of the collector 25.

同図から明らかな如く、分離膜21はバーズビークがほ
とんどなく、はぼ垂直に形成されている。
As is clear from the figure, the separation membrane 21 has almost no bird's beak and is formed almost vertically.

そのため、エミッタ29の側面は完全に絶縁物21で被
覆されており、さらにエミッタ29の底面のフラット部
分のみベース28と接した構造を有している。
Therefore, the side surfaces of the emitter 29 are completely covered with the insulator 21, and furthermore, only the flat portion of the bottom surface of the emitter 29 is in contact with the base 28.

以下、第3図をもとに本発明に係る製造方法を説明する
。
Hereinafter, the manufacturing method according to the present invention will be explained based on FIG.

(a)  n+埋込層33が形成されたp形基板34上
にn形エピタキシャル層35を形成する。この後、エピ
タキシャル層acs 上に5io23s。
(a) An n-type epitaxial layer 35 is formed on a p-type substrate 34 on which an n+ buried layer 33 is formed. After this, 5io23s on the epitaxial layer ACS.

5i3N437を順次形成する。ココテ、b 1023
6は5i3N437の応力を緩和する膜である。
5i3N437 is sequentially formed. Kokote, b 1023
6 is a film that relieves the stress of 5i3N437.

通常これはパット” S t 02と呼ばれる。This is usually called ``Put'' S t 02.

(1))  S i3N437上にレジスト38を島領
域となる部分に被覆し、レジスト38をマスクとして、
分離領域となる部分上のパッドb * 0236 +b
13N43yをエツチングする。さらに、同じレジスト
マスク38でエピタキシャル層36を反応性スパノタエ
ミテング法を用いて垂直にエツチングする。反応性スパ
ノタエノテング法は異方性エッチが可能となるので、レ
ジストマスク38に対して横方向のエツチングは進まず
、はぼ垂直にエツチングされることになる。
(1)) A resist 38 is coated on the Si3N437 to form an island region, and the resist 38 is used as a mask.
Pad on the part that will become the separation area b * 0236 +b
Etch 13N43y. Furthermore, the epitaxial layer 36 is vertically etched using the same resist mask 38 using a reactive spanometer emitter method. Since the reactive sputter etching method enables anisotropic etching, etching does not proceed in the lateral direction with respect to the resist mask 38, but etching occurs almost perpendicularly to the resist mask 38.

(c)次に、レジスト膜38を除去した後、露出したエ
ピタキシャル層36を酸化して第2のバッドb iO2
39を側面に形成する。さらに、全面に第2のb s 
3N440を形成した後、反応性のスバノタエノテング
法を用いて垂直エツチングを行ない、35−1の側面の
みに第2のパン)”5in239、第2 Ob 13N
440を残す。
(c) Next, after removing the resist film 38, the exposed epitaxial layer 36 is oxidized to form a second pad b iO2
39 is formed on the side. Furthermore, a second b s is applied to the entire surface.
After forming 3N440, vertical etching was performed using a reactive etching method to form a second pan on only the sides of 35-1.
440 left.

(d) 5i3N436及び第2 (7) b i3N
 a 40をマスクとして、酸化を行ない絶縁分離膜4
1を形成する。この分離[41の深さはn 埋込33に
接するように形成する。この場合、島領域36−1の側
面に耐酸化性40(第2の5i3N4)が形成されてい
るので、島領域に酸化膜41が入り込壕ない。酸化エピ
タキシャル層35の垂直方向のみに進む。よって、分離
酸化膜41の側面は基板34に対して垂直な面で島領域
35−1と接することになる。さらに、横方向の入り込
みがないのでバーズビークを生じることがない。
(d) 5i3N436 and 2nd (7) b i3N
Using a 40 as a mask, oxidation is performed to form the insulating isolation film 4.
Form 1. The depth of this separation [41] is formed so as to be in contact with the buried portion 33. In this case, since the oxidation-resistant film 40 (second 5i3N4) is formed on the side surface of the island region 36-1, the oxide film 41 does not penetrate into the island region. Proceed only in the vertical direction of the oxidized epitaxial layer 35. Therefore, the side surface of the isolation oxide film 41 comes into contact with the island region 35-1 on a plane perpendicular to the substrate 34. Furthermore, since there is no lateral intrusion, bird's beaks do not occur.

(e)  S i3N437を選択的に除去し、酸化性
雰囲気で熱処理することにより、ベースとコレクタを分
離する酸化膜42を形成する。メース43はレジスト等
をマスクとしてイオン注入により選択的に形成する。
(e) By selectively removing Si3N437 and performing heat treatment in an oxidizing atmosphere, an oxide film 42 separating the base and collector is formed. The mace 43 is selectively formed by ion implantation using a resist or the like as a mask.

(1)全面に多結晶5i44を堆積させる。次に513
N446を堆積させ、部分的にエミッタとなる領域46
−1ベースコンタクトとなる領域45−2.  コレク
タコアタクトとなる領域46−3のSi3N4を残す。
(1) Deposit polycrystalline 5i44 on the entire surface. Next 513
Region 46 where N446 is deposited and partially becomes an emitter
-1 base contact region 45-2. Si3N4 in the region 46-3 which becomes the collector coretact is left.

(g)  5t3N445をマスクとして多結晶514
4のエッチを行ない、さらにベースとエミッタ間のベー
ス43を除去する。次に、5i3N446−1.45−
3をマスクとして選択酸化を行ないエミッタとベースコ
ンタクトを分離するBE分離膜46を形成する。このB
E分離膜46も浅く形成されるので、基板34に対して
ほぼ垂直になる。ここで、44−1.44−2.44−
3はそれぞれエミッタ、ベース、コレクタのコンタクト
用の多結晶Siである。次に、多結晶S i 44−1
.44−3を露出させ、その他の表面はレジスト等で被
覆する。この後、多結晶S i 44−1.44−3に
へ8等の不純物をイオン注入し、レジストを除去した後
熱処理して、エミッタ47.コレクタコンタクト48を
形成する。この時エミッタ47の側面はb 102膜4
6及び41によって完全に被覆されることになる。さら
に、その側面b 102膜46及び41は基板34に対
して垂直な形状を有しているので、エミッタ47はその
底面部のみが接することになりその底面部は平坦になる
。したがってその直下に形成される活性ベースは均一な
幅になる。
(g) Polycrystalline 514 using 5t3N445 as a mask
4 is performed, and the base 43 between the base and the emitter is further removed. Next, 5i3N446-1.45-
Selective oxidation is performed using 3 as a mask to form a BE isolation film 46 that separates the emitter and base contacts. This B
Since the E separation film 46 is also formed shallowly, it is almost perpendicular to the substrate 34. Here, 44-1.44-2.44-
3 is polycrystalline Si for emitter, base, and collector contacts, respectively. Next, polycrystalline Si 44-1
.. 44-3 is exposed, and the other surfaces are covered with resist or the like. Thereafter, an impurity such as 8 is ion-implanted into the polycrystalline Si 44-1.44-3, the resist is removed, and heat treatment is performed to form the emitter 47. A collector contact 48 is formed. At this time, the side surface of the emitter 47 is b 102 film 4
6 and 41. Furthermore, since the side faces b 102 films 46 and 41 have a shape perpendicular to the substrate 34, only the bottom surface of the emitter 47 comes into contact with the emitter 47, so that the bottom surface becomes flat. Therefore, the active base formed directly below has a uniform width.

(h)  コレクタコンタクト48上の多結晶S i 
44−3をすくなくともレジスト等で被覆した後、低エ
ネルギー、高ドーズでボロン等の不純物をイオン注入し
てその後アニールし高濃度の不活性ベース49を形成す
る。この時、エミツタ47直下周辺にのみ高濃度の不活
性ベース49が形成され、直接エミッタの底面及び側面
と接することがない。特に、エミッタ47の側面の厚い
酸化膜41と接している部分は分離酸化膜41がバーズ
ビーブなく、そして基板34に対して垂直に形成されて
いるので、高濃度のボロンがエミッタ47の側面、及び
底面から入り込まない0 (i)  エミッタ電極50.ベース電極61.コレク
タ電極52を形成する。
(h) Polycrystalline Si on collector contact 48
After covering 44-3 with at least a resist or the like, an impurity such as boron is ion-implanted at low energy and high dose, followed by annealing to form a highly concentrated inert base 49. At this time, a highly concentrated inert base 49 is formed only in the vicinity directly below the emitter 47, and does not come into direct contact with the bottom and side surfaces of the emitter. In particular, since the isolation oxide film 41 is formed perpendicularly to the substrate 34 without bird's bead on the side surface of the emitter 47 in contact with the thick oxide film 41, a high concentration of boron is applied to the side surface of the emitter 47 and 0 (i) Emitter electrode 50 that does not enter from the bottom. Base electrode 61. A collector electrode 52 is formed.

本発明の製造方法によ多形成されたバイポーラトランジ
スタは以下に述べる効果を有する。
The bipolar transistor formed by the manufacturing method of the present invention has the following effects.

(1)  エミッタを酸化膜に接して形成してもその分
離酸化膜の側面が基板に対して垂直になっているので、
エミッタの側面は完全に酸化膜で被覆される。そのため
、エミッタ側面の寄生容量が減り高速動作が可能となる
。
(1) Even if the emitter is formed in contact with the oxide film, the side surfaces of the isolation oxide film are perpendicular to the substrate.
The sides of the emitter are completely covered with oxide. Therefore, the parasitic capacitance on the emitter side surface is reduced and high-speed operation is possible.

僻)エミッタの側面が垂直になるので、エミッタ底面が
平坦な構造を有することになる。そのため、エミ”/2
直下全域に渡って均一なベース幅が形成されるので、ト
ランジスタの高周波特性が向上する。さらに電流増幅率
も向上することになる。
Since the side surfaces of the emitter are vertical, the bottom surface of the emitter has a flat structure. Therefore, Emi”/2
Since a uniform base width is formed over the entire area immediately below, the high frequency characteristics of the transistor are improved. Furthermore, the current amplification factor is also improved.

(3)高濃度な外部ベースをイオン注入等を用いてセル
ファラインで形成する場合、エミッタと直接に高濃度外
部ベースが接することがないので、エミッタとベースの
耐圧が劣化することがない。
(3) When a highly doped external base is formed by self-line using ion implantation or the like, the high doped external base does not come into direct contact with the emitter, so the withstand voltage between the emitter and base does not deteriorate.

以上述べたごとく、本発明は高密度化、高速化に適した
バイポーラトランジスタを含む半導体装置を製造出来る
ので工業的価値が高い。
As described above, the present invention has high industrial value because it can manufacture a semiconductor device including a bipolar transistor suitable for high density and high speed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の製造法によるバイポーラトランジスタの
構造断面図、第2図(a)は本発明の製造法によるバイ
ポーラトランジスタの構造断面図、第2図(b)はその
平面図、第3図(−)〜(i)は本発明に係る製造法を
示す工程断面図である。 41・・・・−・分離酸化膜、42−−−−−−−−コ
レクターベース分離酸化膜、43−−−−−−一活性ベ
ース、46−−−−−・エミッターベース分離酸化膜、
47−−−−−−−エミノタ、48−−−−−−−−コ
レクタコンタクト、49−−−一一一不活性ベース。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名@3
I51 @ 3 図
FIG. 1 is a cross-sectional view of the structure of a bipolar transistor manufactured by the conventional manufacturing method, FIG. 2(a) is a cross-sectional view of the structure of a bipolar transistor manufactured by the manufacturing method of the present invention, FIG. (-) to (i) are process cross-sectional views showing the manufacturing method according to the present invention. 41--Isolation oxide film, 42--Collector base isolation oxide film, 43--Active base, 46--Emitter base isolation oxide film,
47--------Eminota, 48-----Collector contact, 49--111 inert base. Name of agent: Patent attorney Toshio Nakao and 1 other person @3
I51 @ 3 Figure

Claims (2)

【特許請求の範囲】[Claims] (1)半導体層の活性領域形成部分上に耐酸化性膜を形
成する工程と、前記活性領域形成部分以外の前記半導体
層を所定量エツチングする工程と、前記耐酸化性膜をマ
スクにして前記半導体層の露出部分を酸化して、前記活
性領域形成部にほぼ垂直に分離酸化膜を形成する工程と
、前記分離酸化膜に−り面が接する様にエミッタを形成
する工程を含む半導体装置の製造方法。
(1) A step of forming an oxidation-resistant film on the active region forming portion of the semiconductor layer, a step of etching a predetermined amount of the semiconductor layer other than the active region forming portion, and etching the oxidation-resistant film using the oxidation-resistant film as a mask. A semiconductor device comprising the steps of: oxidizing an exposed portion of a semiconductor layer to form an isolation oxide film substantially perpendicular to the active region forming portion; and forming an emitter so that its angled surface is in contact with the isolation oxide film. Production method.
(2)所定量エツチングされた半導体層側面に耐酸化性
膜を形成した後、前記半導体層の露出部分を酸化する特
許請求の範囲第1項に記載の半導体装置の製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein an oxidation-resistant film is formed on the side surface of the semiconductor layer that has been etched by a predetermined amount, and then the exposed portion of the semiconductor layer is oxidized.
JP57026247A 1981-12-08 1982-02-19 Preparation of semiconductor device Pending JPS58142575A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57026247A JPS58142575A (en) 1982-02-19 1982-02-19 Preparation of semiconductor device
US06/660,255 US4563227A (en) 1981-12-08 1984-10-12 Method for manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57026247A JPS58142575A (en) 1982-02-19 1982-02-19 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58142575A true JPS58142575A (en) 1983-08-24

Family

ID=12187954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57026247A Pending JPS58142575A (en) 1981-12-08 1982-02-19 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58142575A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147572A (en) * 1984-12-20 1986-07-05 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147572A (en) * 1984-12-20 1986-07-05 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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