JPS58165366A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simultaneously change the resistance values of an internal wiring pattern and a resistance element by a method wherein a metallic silicide film of low resistance is used for the wiring for electrode pulling-up, or in a gate circuit. CONSTITUTION:An Mo film 11 is formed over the entire surface, and a heat treatment is performed in an N atmosphere. The Mo film and Si on apertures 7 and 7' are made to react by this heat treatment resulting in the formation of an Mo silicide film 12. The Mo film 11 is remove by phosphoric acid, then a heat treatment is performed, and accordingly an Si oxide film 13 is formed on the Mo silicide film 12. The Si oxide film 13 is ethed, and thus apertures 14 and 14' are formed to connect to the wiring of aluminum, etc. Electrode wirings 15 and 16 of aluminum, etc., and a wiring 17 are formed on the apertures 14 and 14', and at a desired position.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a large-scale semiconductor device having a resistive element.

Among the methods of forming a resistance element on a semiconductor substrate, a method of doping a desired amount of impurities and utilizing the resistance of single crystal silicon at that time has been widely used.

In this method, for example, single crystal silicon is selectively doped with p-type impurities (impurity diffusion layer 2 x 1018cIIL-
3) L, that area is to be used as a resistance element, the surface of the single crystal silicon is covered with an insulator, only the insulator at both ends of the area of the resistance element is removed, and a wiring material such as aluminum is applied to that part. It is used as an electrode of a resistance element. At this time, the resistance value can be determined by the method of removing the insulator, that is, by the size of the gap between the insulators between the electrodes.

By the way, in integrated circuits, it is often necessary to realize circuits of the same type with different circuit currents using the same mask pattern as much as possible, or to change the resistance value with as few mask pattern modifications as possible due to changes in circuit design. .

How such cases have been dealt with in the past will be explained using drawings. , Figs. 1(a) and 1(b) show 1. in a conventional semiconductor device. : A cross-sectional view schematically showing the structure of a resistive element forming region. In the figure, 1tri''! 'J-con substrate, 2 is a buried layer, 6 is a silicon epitaxial layer, 4 is an impurity diffusion layer for resistance element, 5 is a silicon oxide film, 6 is a silicon nitride film, 7.7' is an opening, 8.8' , 9 indicates an electrode (wiring) for a resistive element, and 10 indicates an electrode gap.

As shown in FIG. 1(a), a silicon oxide film 5. Openings 7 and 7' for pulling up the electrodes of the resistance element are formed in an insulator such as a silicon nitride film 6, and electrodes 8 and 9 made of aluminum or the like are formed thereon. In forming a resistor by such a conventional method, in order to change the resistance value for the above purpose, two masks are used: a mask pattern for the opening 7.7' and a mask pattern for the electrode (aluminum wiring) 8.9. Change or modify the hole 7' and the wiring 8
It was necessary to change the electrode gap 10 by moving the electrode left and right.

Therefore, methods have also been proposed in which only one mask is required to be changed or modified. That is, as shown in FIG. 1(b), the mask pattern is changed in advance so that the electrode 8' is made larger, and only the mask pattern for the opening is changed to move the opening 7' from side to side. The resistance value can be changed by changing the resistance value. In this method, only one mask is required to be changed, but the electrode 8' is provided closest to the end of the other electrode 9, and other wiring (for example, inter-gate connection wiring, etc.) is provided in the electrode gap 10. Since it cannot pass through, the area of the circuit and even the LSI often becomes large. Further, when it is absolutely necessary to provide wiring in the electrode gap 10, the electrode 8' cannot be made very large, and therefore the range in which the resistance value can be changed by changing only the position of the aperture 7' becomes very small.

Furthermore, when changing the circuit current or changing the circuit design is not just a modification of the resistance value as described above, but also requires changing the wiring of the circuit elements, the method shown in Figure 1 (a) above can also be used. It is essential to change the wiring pattern of aluminum, etc., and problems remain, such as the need to change the pattern of two masks.

The present invention was made to solve the problems of the prior art described above, and it is possible to change the resistance value of a resistor element by changing or modifying only one photomask. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not require preparation.

Another object of the present invention is that by changing or modifying only one photomask, it is possible to simultaneously change the internal wiring pattern of, for example, a gate circuit and the resistance value of a resistor element. An object of the present invention is to provide a method for manufacturing a semiconductor device that allows easy design changes.

Still another object of the present invention is to allow wiring other than internal wiring of a circuit to run over resistive elements, etc., without increasing the number of wiring layers or preparing areas without elements for wiring. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be manufactured.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device including a method for forming a resistive element that is well suited to a method for manufacturing a self-aligned high-performance transistor.

In order to achieve the above object, the present invention takes advantage of the fact that a transition metal film and silicon (silicon substrate, polycrystalline silicon film) react through heat treatment to form a low-resistance metal silicide film. The low-resistance metal silicide film is used for raising electrodes of resistive elements on silicon substrates, and also for wiring in gate circuits. In this way, the openings and turns for connecting the metal silicide film to the wiring made of aluminum or the like can be formed into a pattern with a fixed minimum area, and the resistance value of the resistor element can be maintained on the silicon substrate regardless of the wiring pattern made of aluminum or the like. By changing the position of the opening for pulling up the electrode, it is possible to freely change the size of the prepared resistance element within the range. moreover,
If you include the process of forming polycrystalline silicon, you will have the process of leaving polycrystalline silicon in the pattern that is to be used as the wiring in the gate circuit, as well as the process of pulling up the electrode of the resistance element from the silicon substrate and forming the opening that determines the resistance value. Since the steps of 1. and 1. - It becomes possible to change the internal wiring pattern and resistance value of the gate circuit to the same value, making it easier to integrate many types of circuits on the same chip and to change the circuit design.

Hereinafter, the present invention will be explained in detail with reference to Examples.

2(a) to 2(d) are cross-sectional views showing the first embodiment of the semiconductor device of the present invention in the order of manufacturing steps, and FIG. 2(d) shows the structure of the semiconductor device according to the present invention. ° It is. The manufacturing process will be explained in accordance with the order (a) to (d) in the figures. In the figures, the same reference numerals as those mentioned above indicate the same or equivalent parts.

(a): A buried layer 2 was provided on the surface of a silicon substrate 10, and a silicon epitaxial layer 71 layer 5 was formed thereon.

An impurity diffusion layer 4 for a resistance element is formed on the surface of the impurity diffusion layer 4 by a known method.
(The impurity concentration is, for example, 2 x 1 o18 crri-3
) was formed, and further thermal oxidation was performed to form a silicon oxide film 5 (the thickness of the film is, for example, about 50 oi). Next, C on the surface
A silicon nitride film 6 (film thickness, for example, about 1500'k) was formed by the VD method. After that, the normal photo,′,
1 Using etching technology, the area where the electrodes of the resistive element are taken out is silicon nitride, M-con film 6 and silicon oxide film 5, brain.

was etched to form openings 7 and 7'.

(b): Next, a molybdenum film 11 (the film thickness is, for example, about 100 OA) is formed on the entire surface by vapor deposition, sputtering, etc.
Then, in a nitrogen atmosphere at 400-1000℃ for 30 minutes
Heat treatment is performed for 1 hour. Through this heat treatment, the opening 7,
The molybdenum film 7' was reacted with silicon to form a molybdenum silicide film 12.

(C) Second, the molybdenum film 11 is removed with phosphoric acid, and then heat treatment is performed at 600 to 1100°C in an oxygen atmosphere to form a silicon oxide film 13 (about 100 OA thick) on the molybdenum silicide film 12. was formed.

ω) Next, the silicon oxide film 15 is etched using a normal photoetching technique to form openings 14 and 14' for connection to wiring made of aluminum or the like. Further, electrode wires 15, 16 and wires 17 made of aluminum or the like are formed above the openings L4, 14' and at desired positions, thereby completing the resistor element. Here, the wiring 17 is a wiring that is not directly connected to this resistance element, but the resistance element is the electrode wiring 1.
5. ．． 16 can be formed regardless.

FIG. 3 shows the semiconductor device of the first embodiment [FIG. 2(d)]
] is a cross-sectional view showing a modification example. This is a case where the resistance value is to be minimized, but by changing only the openings 7' in the silicon oxide film 5 and the silicon nitride film 6, the patterns of the electrode wiring 15, 16 and the wiring 17 can be changed.
The resistance value of the resistance element can be minimized without changing the turns of the openings 14, 14'. This was not possible with the conventional method as shown in FIG. In order to allow it to pass through, the resistance value cannot be minimized.

Note that in the method of this embodiment (Figs. 2 and 3), normally (
In addition to the method shown in Figure 1), extra steps such as silicide formation and oxidation of the silicide film are required, but if combined with a high-performance self-aligned transistor that uses this silicide film formation, this method can be implemented. In the example shown in Figure 4 (a), all the steps added to the normal resistance element formation can be shared with the steps for forming the transistor, so there is almost no need for any newly added steps for the entire integrated circuit process. - (f) are cross-sectional views showing a second embodiment of the semiconductor device of the present invention in the order of manufacturing steps, and (f) of the same figure shows the structure of the semiconductor device according to the present invention. The manufacturing process will be explained in accordance with the order (a) to (f) in the figures.

(a): A buried layer 2 is provided on the surface of a silicon substrate 1, and a silicon epitaxial layer 5 is formed thereon.

A silicon oxide layer 18 for element isolation and an impurity diffusion layer 4 for resistive elements were formed on this substrate by a known method, and a silicon oxide film 5 was further provided on the surface.

(b) Second, a silicon nitride film 6 is formed on the entire surface by the CVD method, and a polycrystalline silicon film 19 (for example, about 400 OA thick by the CVD method) is further formed thereon.

Then, the polycrystalline silicon layer 19 is left only in the region above the silicon oxide layer 18 for element isolation, and the other portions are removed by etching.

(C): Next, the internal wiring pattern of the gate circuit and the electrode pulling phase of the resistor element were etched in one day using a photoetching technique using a photomask.

First, the polycrystalline silicon film 19 which is to become the electrode wiring for the resistor element and the internal wiring of the cable circuit is left, and the polycrystalline silicon film in the area 20 other than these is removed by etching. At this time, in the region 21 where the resistor element is to be formed, there is a turn for the electrode of the resistor element, but since the polycrystalline silicon has already been removed and no remaining polycrystalline silicon remains, the region 21 is not affected at all.

(d): Next, using a photoetching technique, the silicon nitride film 6 and the silicon oxide film 5 in the region from which the electrodes of the resistive element are taken out are etched to form openings 7 and 7'. After that, a molybdenum film 11 (thickness is, for example, about 100 mm) is applied.
) is formed on the entire surface by vapor deposition, sputtering, etc.

(e) Second, heat treatment is performed in a nitrogen atmosphere to form the hole 7.
, 7' and silicon, and at the same time, the polycrystalline silicon film 19 and molybdenum film 11 are reacted to form a molybdenum silicide film 12.

Next, after removing the remaining molybdenum film 11 with phosphoric acid, the remaining molybdenum film 11 is removed in an oxygen atmosphere. IJ7'
A silicon oxide film 13 is formed on the 7"y 71), 1.Y1°-□,.

(f) Secondarily, an opening pattern 14.14' for connecting the molybdenum silicide film 12 and the aluminum wiring is formed, and further aluminum electrode wiring 15.16 and wiring (inter-gate connection wiring) 17.17' are formed. Form.

As a result, internal wiring 22, 23 of the resistance element, internal wiring 24 of the gate circuit, aluminum electrode wiring 15° 16,
Wiring 17.17' has been completed. Furthermore, the connection between the internal wiring 25 of the resistance element using the molybdenum silicide film and the aluminum wiring was completed.

FIG. 5 shows the semiconductor device of the second embodiment [FIG. 4(f)
] is a cross-sectional view showing a modification example. This is shown in Figure 4 (C)
This is a case where one mask pattern used in the step (d) is changed, and the pattern of the openings 14, 14' and the pattern of the aluminum wiring 15, 16, 17, 17' are as shown in FIG. 4(f). Although it is the same as in the case of FIG. 4(f), the internal wiring of the gate circuit, such as the resistance value of the resistance element and the connection of the resistance element, can be changed from the case of FIG. 4(f).

Furthermore, the aluminum wiring lines 17 and 17' in FIG. 4(f) and FIG. can be run. As a result, it becomes possible to connect gate circuits without increasing the number of aluminum wiring layers and without preparing so-called wiring areas where no elements are placed for running wiring.

Further, like the first embodiment, the method according to this embodiment can be well adapted to a method of manufacturing a high-performance self-aligned transistor using silicide film formation.

Although a molybdenum film is used as the silicide electrode material in the embodiment, it is of course possible to use a transition metal material such as tungsten in the present invention.

As explained above, according to the present invention, it is possible to change the resistance value of a resistor element, the circuit format, or the circuit design by changing only one photomask, thereby greatly increasing the flexibility of integrated circuit design. . In addition, there is no need to make large electrodes to change the resistance value as in the prior art (Fig. 1, 6), and the first layer of aluminum wiring can be run over the gate circuit, reducing the wiring area. It is possible to increase the degree of integration.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are both cross-sectional views of a resistive element formation region in a conventional semiconductor device, and FIGS. 2(a) to (d)
) and FIGS. 4(a) to 4(f) are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention in order of process, and FIG.
(A sectional view showing a modification of φ, FIG. 5 is a sectional view showing a modification of FIG. 4(f). 1...Silicon substrate 2...Buried layer 3...Silicon epitaxial Layer 4... Impurity diffusion layer for resistance element 5... Silicon oxide film 6... Silicon nitride film 7
．． 7'... Opening 11... Molybdenum film (transition metal film) 12... Molybdenum silicide film
13...Silicon oxide film 14, 14'...Opening
15.16... Electrode wiring 17... Wiring
18...Silicon oxide layer for element isolation" 00
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□,,□□1. □・・・ 1'1 Representative Patent Attorney Junnosuke Nakamura 1 Item 2 Item 4 @

Claims (2)

[Claims] (1) A method for manufacturing a t-conductor device having a resistance element, including the following steps. (2) A first step that includes a step of covering the surface of the silicon substrate on which the impurity diffusion layer for resistive element is provided with a silicon oxide film, and then covering it with a silicon nitride film. @ In order to form a resistance element having a desired resistance value, a position for taking out an electrode from the impurity diffusion layer is determined, and the silicon nitride film and silicon oxide film in the region where the electrode is to be provided are removed and a hole is opened. Moderate. θ A step of forming a transition metal film on the entire surface of the silicon substrate including the opening. A step of causing the transition metal film and silicon to react by O heat treatment to form a metal silicide film on and around the opening. ■ A step of oxidizing the metal silicide film to form a silicon oxide film on the surface. (2) The first step includes the steps of covering the surface of the silicon substrate on which the impurity diffusion layer for the resistance element is provided with a silicon oxide film, and then covering it with a silicon nitride film, and forming a polycrystalline silicon film on the silicon nitride film. 2. The method of manufacturing a semiconductor device according to claim 1, comprising a step of forming the polycrystalline silicon film and a step of leaving the polycrystalline silicon film only in a region to be used as a wiring for electrical connection.